xr17c152im Exar Corporation, xr17c152im Datasheet - Page 24

• Manufacturer Part Number: xr17c152im
• Description: 5v Pci Bus Dual Uart
• Manufacturer: Exar Corporation

XR17C152
5V PCI BUS DUAL UART
The THR and RHR register address for channel 0 to channel 1 is shown in
for each channel 0 tand 1 are located sequentially at address 0x0000 and 0x0200. Transmit data byte is
loaded to the THR when writing to that address and receive data is unloaded from the RHR register when
reading that address. Both THR and RHR registers are 16C550 compatible in 8-bit format, so each bus
operation can only write or read in bytes.
There are 2 UARTs [channels 1:0] in the 152. Each has its own 64-byte of transmit and receive FIFO, a set of
16550 compatible control and status registers, and a baud rate generator for individual channel data rate
setting. Eight additional registers per UART were added for the EXAR enhanced features.
Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The
prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide
the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further
divides this clock by a programmable divisor between 1 and (2
the serial data rate. The sampling clock is used by the transmitter for data bit shifting and receiver for data
sampling. The BRG divisor (DLL and DLM registers) defaults to a random value upon power up. Therefore, the
BRG must be programmed during initialization to the operating data rate.
Programming the Baud Rate Generator Registers DLM and DLL provides the capability for selecting the
operating data rate.
3.2
4.0 UART
4.1
FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR
AND RHR IN 8-BIT FORMAT
Programmable Baud Rate Generator
T
ABLE
F
IGURE
CH0 0x000 Read RHR
CH0 0x000 Write THR
CH1 0x200 Write THR
CH1 0x200 Read RHR
XTAL1
XTAL2
8: T
Table 9
9. B
RANSMIT AND
THR and RHR Address Locations For CH0 to CH1 (16C550 Compatible)
AUD
shows the standard data rates available with a 14.7456 MHz crystal or external
R
Crystal
Buffer
Osc/
ATE
R
G
ECEIVE
To Channel 1
ENERATOR
Bit-7
Bit-7
Bit-7
Bit-7
D
Divide by 4
Divide by 1
ATA
Prescaler
Prescaler
Bit-6
Bit-6
Bit-6
Bit-6
R
EGISTER IN
24
Bit-5
Bit-5
Bit-5
Bit-5
MCR Bit-7=0
MCR Bit-7=1
(default)
Bit-4
Bit-4
Bit-4
Bit-4
B
16
YTE FORMAT
Baud Rate
DLL and DLM
Generator
-1) to obtain a 16X or 8X sampling clock of
Registers
Logic
Bit-3
Bit-3
Bit-3
Bit-3
Bit-2
Bit-2
Bit-2
Bit-2
Table 8
, 16C550
Rate Clock to
and Receiver
Bit-1
Bit-1
Bit-1
Bit-1
Transmitter
16X or 8X
Sampling
below. The THR and RHR
COMPATIBLE
Bit-0
Bit-0
Bit-0
Bit-0
áç
áç
áç
áç
REV. 1.2.0