xr16c2850im Exar Corporation, xr16c2850im Datasheet - Page 26

• Manufacturer Part Number: xr16c2850im
• Description: Dual Uart With Tx And Rx Fifo Counters, 128 Bytes Of Fifos And Automatic Rs-485 Half Duplex Control
• Manufacturer: Exar Corporation

XR16C2850
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
ISR[0]: Interrupt Status
•
•
ISR[5:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See
4.4.1, Interrupt Generation:” on page 25
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
•
•
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•
•
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•
•
4.5
P
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition).
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
Logic 0 = No receive FIFO reset (default).
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
L
RIORITY
EVEL
7
-
FIFO Control Register (FCR) - Write-Only
B
IT
1
0
-5
B
IT
0
0
-4
ISR R
B
EGISTER
IT
T
0
0
ABLE
-3
9: I
B
S
IT
TATUS
0
0
-2
NTERRUPT
and
B
B
ITS
IT
“Section 4.4.2, Interrupt Clearing:” on page 25
0
0
-1
S
OURCE AND
26
B
IT
0
1
-0
CTS#, RTS# change of state
None (default)
P
RIORITY
L
EVEL
S
OURCE OF INTERRUPT
Table
9). See
xr
for details.
REV. 2.1.3
“Section