xr16l651im Exar Corporation, xr16l651im Datasheet - Page 16

• Manufacturer Part Number: xr16l651im
• Description: 2.25v To 5.5v Uart With 32-byte Fifo
• Manufacturer: Exar Corporation

XR16L651
2.25V TO 5.5V UART WITH 32-BYTE FIFO
The receiver section contains an 8-bit Receive Shift Register (RSR) and 32 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates
every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit,
an internal receiver counter starts counting at the 16X clock rate. After 8 clocks the start bit period should be at
the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating
the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits
and stop bits are sampled and validated in this same manner to prevent false framing. If there were any
error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the
receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the data
byte in the RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay
until it reaches the FIFO trigger level (XFR bit-3). Furthermore, data delivery to the host is guaranteed by a
receive data ready time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus
12 bits time. This is equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0.
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 32 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
F
2.10
2.10.1
IGURE
11. R
Receiver
Receive Holding Register (RHR) - Read-Only
ECEIVER
and E rrors
D ata B yte
16X C lock
R eceive
O
PERATION IN NON
LS R bits
T ags in
E rror
4:2
-FIFO M
R eceive D ata S hift
R egister (R S R )
H olding R egister
R eceive D ata
ODE
(R H R )
16
V alidation
D ata B it
R H R Interrupt (IS R bit-2)
R e ce ive D a ta C ha rac te rs
R X F IF O 1
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REV. 1.3.0