ak4372 ETC-unknow, ak4372 Datasheet - Page 43

• Manufacturer Part Number: ak4372
• Description: Dac With Built-in Pll & Hp-amp
• Manufacturer: ETC-unknow

1) DAC → HP-Amp
(1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
(2) PMVCM, PMPLL, PMDAC, MCKO and M/S bits should be changed to “1” after the PDN pin goes “H”.
(3) The PLL operation is executed when the system clock is input to the MCKI pin.
(4) The PLL lock time is referred to
(5) DALHL and DARHR bits should be changed to “1” after the PLL is locked.
(6) PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pin
(7) Rise time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The rise time up to
(8) Fall time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The fall time down to
(9) Analog output corresponding to the digital input has group delay (GD) of 22/fs(=499μs@fs=44.1kHz).
(10) The ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).
(11) The power supply should be switched off after the headphone-amp is powered down (HPL/R pins become “L”).
MS0684-E-02
Power-Up/Down Sequence (PLL Master mode)
Power Supply
PDN pin
M/S, PMVCM, PMPLL,
PMDAC, MCKO bits
MCKI pin
MCKO pin
BICK, LRCK pins
DAC Internal
SDTI pin
DALHL,
DARHR bits
PMHPL,
PMHPR bits
MUTEN bit
ATTL7-0
ATTR7-0 bits
HPL/R pin
more. The PDN pin should be set to “H” at least 150ns after power is supplied.
MCKO pins.
is 2.2μF) after the DALHL and DARHR bits are changed to “1”.
VCOM/2 is t
VCOM/2 is t
PMHPL and PMHPR bits should be changed to “0” after HPL and HPR pins go to HVSS. After that, the
DALHL/DARHR bits should be changed to “0”.
When AVDD and DVDD are supplied separately, DVDD should be powered-down at the same time or after AVDD.
State
r
f
Figure 36 Power-up/down sequence of DAC and HP-amp (Don’t care: except Hi-Z)
= 70k x C(typ). When C=1μF, t
= 60k x C(typ). When C=1μF, t
Don’t care
Don’t care
PD
Unstable
Don’t care
(1)
>150ns
Unstable
Unstable
00H(MUTE)
(2) >0
“L”
(3)
(4) ~20ms
(7)
(5) >0
Table
(6) >2ms
(9) GD (10) 1061/fs
Normal Operation
4. After the PLL is locked, each clock is output from BICK, LRCK and
FFH(0dB)
r
f
= 70ms(typ).
= 60ms(typ).
(9) (10)
- 43 -
Unstable
00H(MUTE)
(8)
Don’t care
Don’t care
Unstable
Unstable
PD
Unstable
(4) ~20ms
(7)
(5) >0
(6) >2ms
Normal Operation
(9) (10)
FFH(0dB)
(9) (10)
00H(MUTE)
Don’t care
Don’t care
Don’t care
(8)
PD
[AK4372]
(11)
2008/12