ak4372 ETC-unknow, ak4372 Datasheet - Page 12

• Manufacturer Part Number: ak4372
• Description: Dac With Built-in Pll & Hp-amp
• Manufacturer: ETC-unknow

Parameter
Control Interface Timing (I
Power-down & Reset Timing
Note 22. Except AC coupling.
Note 23. Pulse width to ground level when the MCKI pin is connected to a capacitor in series and a resistor is connected
Note 24. Refer to “Serial Data Interface”.
Note 25. Min is longer value between 312.5ns or 1/(64fs) except for PLL Mode, PLL4-0 bits = “01110”, “01111”.
Note 26. BICK rising edge must not occur at the same time as LRCK edge.
Note 27. CCLK rising edge must not occur at the same time as CSN edge.
Note 28. I
Note 29. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 30. When power-up, the AK4372 can be reset by bringing PDN pin = “H” from “L”.
MS0684-E-02
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Capacitive Load on Bus
Pulse Width of Spike Noise Suppressed by Input Filter
PDN Pulse Width
to ground. (Refer to
2
C is a registered trademark of Philips Semiconductors.
(Note
30)
Figure
2
C Bus mode):
3.)
(Note
29)
(Note
28)
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tHD:DAT
tHD:STA
tSU:DAT
tSU:STA
tSU:STO
Symbol
tHIGH
tLOW
fSCL
tBUF
tPD
tSP
Cb
tR
tF
min
150
1.3
0.6
1.3
0.6
0.6
0.1
0.6
0
0
-
-
-
-
typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
max
400
400
0.3
0.3
50
-
-
-
-
-
-
-
-
-
[AK4372]
2008/12
Units
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
ns
ns