ak4372 ETC-unknow, ak4372 Datasheet - Page 18

• Manufacturer Part Number: ak4372
• Description: Dac With Built-in Pll & Hp-amp
• Manufacturer: ETC-unknow

When PLL reference clock input is the LRCK or BICK pin, the sampling frequency is selected by FS3-0 bits.
■
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In master mode (M/S bits = “1”), the LRCK and BICK pins output “L” before the PLL is locked by setting PMPLL =
PMDAC bits = “0”
MCKO bit = “0”, the MCKO pin outputs “L”. After the PLL is locked, the LRCK and BICK start outputting the clocks
(Table
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In slave mode (M/S bits = “0”), an invalid clock is output from the MCKO pin when MCKO bit = “1”, before the PLL is
locked by setting PMPLL = PMDAC bits = “0”
PLL is locked, the MCKO pin starts outputting the clocks
MS0684-E-02
MCKI pin
MCKO pin
BICK pin
LRCK pin
MCKI pin
MCKO pin
BICK pin
LRCK pin
PLL Unlock State
Table 6. Setting of Sampling Frequency (PLL reference clock input is LRCK or BICK pin) (N/A: Not available)
7).
Others
Mode
0
1
2
3
4
MCKO bit = “1”: Output
Power Up
(PMDAC bit= PMPLL bit= “1”)
Refer to
MCKO bit = “0”: “L”
BF bit = “1”: 64fs output
BF bit = “0”: 32fs output
Output
Power Up
(PMDAC bit= PMPLL bit= “1”)
Refer to
MCKO bit = “0”: “L”
MCKO bit = “1”: Output
FS3 bit
“1”. At that time, the MCKO pin outputs an irregular frequency clock at MCKO bit = “1”. When
Table
Table
1
1
1
1
1
Input
Input
4.
4.
Table 7. Clock Operation in Master mode (PLL mode)
Table 8. Clock Operation in Slave mode (PLL mode)
FS2 bit
0
0
0
0
1
Others
FS1 bit
Power Down
(PMDAC bit= PMPLL bit= “0”)
Input or
fixed to “L” or “H” externally
Power Down
(PMDAC bit= PMPLL bit= “0”)
Input or
fixed to “L” or “H” externally
Master Mode (M/S bit = “1”)
Fixed to “L” or “H” externally
Fixed to “L” or “H” externally
Slave Mode (M/S bit = “0”)
0
0
1
1
0
“1”. When MCKO bit = “0”, the MCKO pin outputs “L”. After the
(Table
- 18 -
FS0 bit
0
1
0
1
0
L
L
L
L
9).
Sampling Frequency Range
32kHz < fs ≤ 48kHz
24kHz < fs ≤ 32kHz
16kHz < fs ≤ 24kHz
12kHz < fs ≤ 16kHz
8kHz ≤ fs ≤ 12kHz
N/A
PLL Unlock
Refer to
MCKO bit = “0”: L
MCKO bit = “1”: Unsettling
PLL Unlock
Refer to
MCKO bit = “0”: L
MCKO bit = “1”: Unsettling
Input or
Fixed
externally
Input or
Fixed
externally
Table
Table
to
to
“L”
“L”
L
L
4.
4.
(default)
or
or
[AK4372]
(Table
“H”
“H”
2008/12
6)