xrt94l33 Exar Corporation, xrt94l33 Datasheet - Page 6

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xrt94l33

Manufacturer Part Number
xrt94l33
Description
Multi-channel, Multi-function Device Aggregates 3 Ds3/e3/sts-1 Into Oc3/stm-1
Manufacturer
Exar Corporation
Datasheet

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XRT94L33
Rev.1.2.0.
AC18
P
IN
#
S
IGNAL
PRD_L/
DS*/
WE*
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
N
AME
I/O
I
S
T
TTL
IGNAL
YPE
READ Strobe /Data Strobe:
The exact function of this input pin depends upon which mode
the Microprocessor Interface has been configured to operate in,
as described below.
Intel-Asynchronous Mode – RD* - READ Strobe Input:
If the Microprocessor Interface is operating in the Intel-
Asynchronous Mode, then this input pin will function as the RD*
(Active Low READ Strobe) input signal from the Microprocessor.
Once this active-low signal is asserted, then the XRT94L33 will
place the contents of the addressed register (or buffer location)
on the Microprocessor Bi-directional Data Bus (D[7:0]). When
this signal is negated, the Data Bus will be tri-stated.
Motorola-Asynchronous (68K) Mode – DS* - Data Strobe
Input:
If the Microprocessor Interface is operating in the Motorola
Asynchronous Mode, then this input will function as the DS*
(Data Strobe) input signal.
PowerPC 403 Mode – WE* - Write Enable Input:
If the Microprocessor Interface is operating in the PowerPC 403
Mode, then this input pin will function as the WE* (Write Enable)
input pin.
Anytime the Microprocessor Interface samples this active-low
input signal (along with CS* and WR*/R/W*) also being asserted
(at a logic level) upon the rising edge of PCLK, then the
Microprocessor Interface will (upon the very same rising edge of
PCLK) latch the contents on the Bi-Directional Data Bus (D[7:0])
into the “target” on-chip register or buffer location within the
XRT94L33.
6
D
ESCRIPTION
xr

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