xrt94l33 Exar Corporation, xrt94l33 Datasheet - Page 439

• Manufacturer Part Number: xrt94l33
• Description: Multi-channel, Multi-function Device Aggregates 3 Ds3/e3/sts-1 Into Oc3/stm-1
• Manufacturer: Exar Corporation

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
• UTOPIA Level 1 or 2
The user can configure the Receive UTOPIA Interface block (within the XRT94L33) to operate in the
appropriate UTOPIA Level, by writing the appropriate value into Bit 7 (UTOPIA Level) within the “Receive
UTOPIA Control Register”, as depicted below.
Receive UTOPIA Control Register – Byte 0, Address = 0x0403
Setting this bit-field to “0” configures the Receive UTOPIA Interface block to support “UTOPIA Level 3”
signaling. Conversely, setting this bit-field to “1” configures the Receive UTOPIA Interface block to support
the “UTOPIA Levels 1 and 2” form of signaling. A description of the operation of the Receive UTOPIA
Interface block, for UTOPIA Level 1, 2 and 3 operation is presented below.
UTOPIA Level 1 and 2 Operation
UTOPIA Level 3 Operation
S
The UTOPIA data bus width can be selected to be either 8 or 16 bits by writing the appropriate data into Bits
3 and 2 (Receive UTOPIA Data Bus Width[1:0]) within the “Receive UTOPIA Control” Register, as depicted
below.
Receive UTOPIA Control Register – Byte 0, Address = 0x0403
If the user chooses a UTOPIA Data Bus width of 8 bits, then only the Receive UTOPIA Data outputs:
RxUData[15:8] will be active. (The output pins: RxUData[7:0] will not be active). If the user chooses a
UTOPIA Data bus width of 16 bits, then all of the Receive UTOPIA Data output: RxUData[15:0] will be active.
The following table relates the value of Bits 2 and 3 (Receive UTOPIA Data Bus Width[1:0]) within the
Receive UTOPIA Control Register, to the corresponding width of the UTOPIA Data bus.
Table 20 The Relationship between the contents of “Receive UTOPIA Data Bus Width[1:0] within the
Receive UTOPIA Control Register and the operating width of the UTOPIA Data Bus
R
ELECTING THE
ECEIVE
UTOPIA
UTOPIA
Level
Level
B
B
R/W
R/W
IT
IT
X
1
7
7
W
UTOPIA D
IDTH
00
01
10
11
[1:0]
UTOPIA D
Multi-PHY
Multi-PHY
Mode
B
ATA
Mode
R/W
B
R/W
IT
0
IT
0
6
B
6
US
ATA
Polling Enable
Back-to-Back
Polling Enable
B
Back-to-Back
US
B
R/W
IT
0
B
R/W
W
IT
5
0
IDTH
5
Direct Status
Direct Status
Access
B
R/W
W
Access
IT
0
B
R/W
IDTH OF
4
IT
0
Not valid (do not use)
439
4
UTOPIA D
In-active:
16 bits
8 bits
Receive UTOPIA Data
Receive UTOPIA Data Bus
B
R/W
IT
X
Bus Width[1:0]
B
R/W
3
IT
X
ATA
3
Width[1:0]
B
US
B
R/W
IT
X
2
B
R/W
IT
X
2
Cell_Size_Sel[1:0]
B
R/W
Cell_Size_Sel[1:0]
IT
1
B
R/W
1
IT
1
1
XRT94L33
Rev.1.2.0.
B
B
R/W
R/W
IT
IT
1
1
0
0