xrt94l33 Exar Corporation, xrt94l33 Datasheet - Page 200

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xrt94l33

Manufacturer Part Number
xrt94l33
Description
Multi-channel, Multi-function Device Aggregates 3 Ds3/e3/sts-1 Into Oc3/stm-1
Manufacturer
Exar Corporation
Datasheet

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XRT94L33
Rev.1.2.0.
STEP 5 – Write the “desired value” for the payload byte (within these Idle Cells) into the “Transmit
ATM Cell – Idle Cell Payload Byte Register; as depicted below.
Transmit ATM Cell – Idle Cell Payload Byte Register (Address = 0xNF1F)
Note:
2.2.6.11
The Transmit ATM Cell Processor block consists of a “Transmit GFC Nibble-Field” Input port. Figure 29
presents the Functional Block Diagram of the “Transmit ATM Cell Processor” block with the “Transmit GFC
Nibble-Field Serial Input Port” block highlighted.
Figure 29: An Illustration of the Functional Block Diagram of the Transmit ATM Cell Processor Block,
with the “Transmit GFC Nibble-Field Serial Input Port” block highlighted
As the name of this port implies, this port permits the user to insert his/her value for the GFC nibble into each
outbound ATM Cell.
B
R/W
P7
IT
7
Each of the 48 bytes, within the Idle Cell Payload will be set to the value written into this register.
Transmit UTOPIA
T
Interface Block
HE
TxFIFO
TxFIFO
T
B
R/W
RANSMIT
P6
Main Data Path
IT
6
GFC N
B
R/W
P5
IT
IBBLE
Generator
Checker
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
Generator
Checker
Parity
Idle Cell
Block
Parity
Idle Cell
Block
-F
IELD
Idle_Cell_Payload_Byte[7:0]
B
R/W
S
P4
IT
ERIAL
4
User Cell
Calculation
HEC Byte
User Cell
Calculation
Insertion
HEC Byte
Filter
Block
Insertion
200
Filter
Block
Block
I
NPUT
Block
&
&
P
B
R/W
P3
ORT
IT
3
Cell Extraction
Cell Insertion
Cell Extraction
Transmit GFC
Cell Insertion
Cell Payload
Processor
Processor
Transmit GFC
Nibble-Field
Cell Payload
Scrambler
Processor
Processor
Buffer/
Nibble-Field
Input Port
Buffer/
Scrambler
Buffer/
Buffer/
Input Port
Block
Block
Block
B
Block
R/W
P2
IT
2
Microprocessor
Microprocessor
STS-3c/STS-12c
Processor Block
B
R/W
To Transmit
Interface
Input Port
P1
Interface
IT
TxGFC
Block
Block
1
POH
xr
B
R/W
P0
IT
0

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