xrt94l33 Exar Corporation, xrt94l33 Datasheet - Page 405

• Manufacturer Part Number: xrt94l33
• Description: Multi-channel, Multi-function Device Aggregates 3 Ds3/e3/sts-1 Into Oc3/stm-1
• Manufacturer: Exar Corporation

xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
When the HEC Byte Verification block is operating in the PRE-SYNC state, it will then begin to sample five (5)
“candidate header bytes” from the data within the incoming data-stream, repeatedly at 53 byte intervals.
During this sampling process, the HEC Byte Verification block will compute and compare its newly computed
“HEC byte value” with that of the fifth (read-in) octet. If the HEC Byte Verification block, while operating in the
PRE-SYNC state, comes across a single invalid cell header byte pattern, then the HEC Byte Verification block
will transition back to the “HUNT” state. However, if the HEC Byte Verification block detects “DELTA”
consecutive valid cell byte headers, then it will transition into the SYNC state.
The SYNC State
Once the HEC Byte Verification block has transitioned into the “SYNC” state, then this means that the
Receive ATM Cell Processor block is “officially” delineation ATM cells. The Receive ATM Cell Processor
block will notify the Microprocessor (and external circuitry) of this transition into the SYNC state by doing all of
the following.
1. It will indicate that it as cleared the LCD defect condition by setting Bit 0 (LCD Defect Declared) and the
Bits 2 and 1 (Cell Delineation Status[1:0]) bit-fields, within the “Receive ATM Cell Processor Block – Receive
ATM Status Register” to “0”, as depicted below.
Receive ATM Cell Processor Block – Receive ATM Status Register (Address = 0xN707)
2. It will generate the “Clearance of LCD Defect Condition” interrupt. The Receive ATM Cell Processor block
will indicate that it is declaring the “Clearance of LCD Defect Condition” Interrupt by doing the following.
Receive ATM Cell Processor Block – Receive ATM Interrupt Status Register – Byte 0 (Address =
0xN70B)
Whenever the HEC Byte Verification block is operating in the SYNC state, it will tolerate a certain number of
errors in the header bytes of the incoming cells. Additionally, in some case, the HEC Byte Verification block
will even attempt to correct some of these errors. However, the occurrence of “ALPHA” consecutive cells with
header byte errors (single or multi-bit) will cause the HEC Byte Verification block to return to the “HUNT”
state. If this were to occur, then the Receive ATM Cell Processor block will notify the external circuitry that it
is not properly delineating cells by doing the following.
Insertion
Interrupt
Receive
Status
B
RUR
B
Cell
R/O
IT
IT
0
0
7
7
-
-
Overflow
Interrupt
Receive
Toggling the “INT*” output pin “low”.
Setting Bit 1 (Clearance of LCD Defect Interrupt Status), within the “Receive ATM Cell
Processor Block – Receive ATM Interrupt Status Register – Byte 0” to “1” as depicted below.
Status
B
FIFO
RUR
B
R/O
IT
0
IT
0
6
6
Unused
Extraction
Overflow
Interrupt
Receive
Memory
Status
B
RUR
Cell
B
IT
R/O
0
IT
0
5
5
Overflow
Insertion
Receive
Memory
Interrupt
Status
B
RUR
Cell
B
IT
0
R/O
IT
0
4
4
405
Detection of
Correctable
HEC Byte
Interrupt
PRBS Lock
Status
Indicator
B
Error
RUR
IT
0
B
R/O
IT
3
0
3
Uncorrectable
Error Interrupt
Detection of
Cell Delineation Status[1:0]
HEC Byte
Status
B
RUR
B
R/O
IT
0
IT
0
2
2
Clearance
Interrupt
of LCD
Defect
Status
B
R/O
B
RUR
IT
0
IT
1
1
1
XRT94L33
LCD Defect
Declaration
Declared
Interrupt
of LCD
Defect
Status
Rev.1.2.0.
B
B
RUR
R/O
IT
0
IT
0
0
0