lf3310 LOGIC Devices Incorporated, lf3310 Datasheet - Page 9

• Manufacturer Part Number: lf3310
• Description: Horizontal / Vertical Digital Image Filter
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
be rounded to any precision required.
Since any 32-bit value may be pro-
grammed into the round registers, the
device can support complex rounding
algorithms as well as standard Half-
LSB rounding. HRSL
which of the sixteen horizontal round
registers are used in the rounding
operation. A value of 0 on HRSL
selects horizontal round register 0. A
value of 1 selects horizontal round
register 1 and so on. HRSL
T
T
ABLE
ABLE
BITS
BITS
11-3
11-7
4-1
0
1
2
0
5
6
2. C
3. C
FUNCTION
ALU Mode
Pass A
Pass B
Reserved
FUNCTION
Odd-Tap Interleave Mode
I/D Register Length
Horizontal Tap Number
Horizontal Data Reversal
Reserved
ONFIGURATION
ONFIGURATION
3-0
determines
3-0
may be
R
R
3-0
EGISTER
EGISTER
DESCRIPTION
0 : A + B
1 : B – A
0 : ALU Input A = 0
1 : ALU Input A = Forward Register Path
0 : ALU Input B = 0
1 : ALU Input B = Reverse Register Path
Must be set to “0”
DESCRIPTION
0 : Odd-Tap Interleave Mode Disabled
1 : Odd-Tap Interleave Mode Enabled
0000: 1 Register
0001: 2 Registers
0010: 3 Registers
0011: 4 Registers
0100: 5 Registers
0101: 6 Registers
0110: 7 Registers
0111: 8 Registers
1000: 9 Registers
1001: 10 Registers
1010: 11 Registers
1011: 12 Registers
1100: 13 Registers
1101: 14 Registers
1110: 15 Registers
1111: 16 Registers
0 : Even Number of Taps
1 : Odd Number of Taps
0 : Data Reversal Enabled
1 : Data Reversal Disabled
Must be set to “0”
changed every clock cycle if desired.
This allows the rounding algorithm to
be changed every clock cycle. This is
useful when filtering interleaved data.
If rounding is not desired, a round
register should be loaded with 0 and
selected as the register used for round-
ing. Round register loading is dis-
cussed in the LF Interface
Horizontal Select
The word width of the horizontal
0 – A
1 – A
DDRESS
DDRESS
200H
201H
9
Horizontal / Vertical Digital Image Filter
TM
section.
filter output is 32-bits. However, only
12-bits may be sent to the filter output.
The horizontal filter select circuitry
determines which 12-bits are passed
(see Table 1). The horizontal select
registers control the horizontal select
circuitry. There are sixteen horizontal
select registers. Each select register
is 5-bits wide and user-programma-
ble. HRSL
sixteen horizontal select registers are
used in the horizontal select circuitry.
A value of 0 on HRSL
zontal select register 0. A value of 1
selects horizontal select register 1 and
so on. HRSL
clock cycle if desired. This allows the
12-bit window to be changed every
clock cycle. This is useful when filter-
ing interleaved data. Select register
loading is discussed in the LF Inter-
face
Horizontal Limiting
An output limiting function is pro-
vided for the output of the horizontal
filter. The horizontal limit registers
determine the valid range of output
values when limiting is enabled (Bit
1 in Configuration Register 5). There
are sixteen 24-bit horizontal limit reg-
isters. HRSL
izontal limit register is used during
the limit operation. A value of 0 on
HRSL
ter 0. A value of 1 selects horizontal
limit register 1 and so on. Each limit
register contains both an upper and
lower limit value. If the value fed
to the limiting circuitry is less than
the lower limit, the lower limit value
is passed as the filter output. If
the value fed to the limiting circuitry
is greater than the upper limit, the
upper limit value is passed as the filter
output. HRSL
every clock cycle if desired. This
allows the limit range to be changed
every clock cycle. This is useful when
filtering interleaved data. When load-
ing limit values into the device, the
upper limit must be greater than the
Video Imaging Products
TM
3-0
section.
selects horizontal limit regis-
3-0
3-0
3-0
determines which of the
3-0
may be changed every
determines which hor-
may be changed
3-0
9/14/2005-LDS.3310-I
selects hori-
LF3310