lf3310 LOGIC Devices Incorporated, lf3310 Datasheet - Page 6

• Manufacturer Part Number: lf3310
• Description: Horizontal / Vertical Digital Image Filter
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
sizes of 3-3, 5-5, and 7-7 (see Figure
7). Data delay elements at the input
of the horizontal filter and the output
of the vertical filter are used to prop-
erly align data so that the orthogonal
kernel is implemented correctly. The
data delays are automatically set to
the correct lengths based on the pro-
grammed length of the line buffers
and the kernel size.
Kernel sizes of 3-3, 5-5, and 7-7 require
that the horizontal filter’s output be
delayed by LB – 2, 2(LB) – 3, and
3(LB) – 4 clock cycles respectively
before being added to the vertical fil-
ter’s output (LB is the programmed
line buffer length). The data delay at
F
F
IGURE
IGURE
H
1
DIN
HV
V
V
11-0
6. O
7. 3-3, 5-5,
1
3
2
H
3
RTHOGONAL
12
LINE BUFFER
LINE BUFFER
LINE BUFFER
LINE BUFFER
LINE BUFFER
LINE BUFFER
LINE BUFFER
H
1
AND
H
2
DELAY
DATA
HV
M
V
V
V
V
7-7 O
1
2
4
5
ODE
3
H
4
RTHOGONAL
H
5
the input of the horizontal filter han-
dles the LB, 2(LB), and 3(LB) delays.
The data delay at the output of the
vertical filter handles the – 2, – 3, and
– 4 delays. For example, if the line
buffers are programmed for a length
of 720 and a 5–5 kernel is selected, the
horizontal filter input data delay will
be 1440 clock cycles and the vertical
filter output data delay will be 3 clock
cycles.
It is important to note that the first
3, 5, or 7 multipliers of the horizontal
and vertical filters must be used in
Orthogonal Mode. If other multipliers
are used, data from the horizontal and
vertical filters will not line up cor-
DELAY
DATA
H
1
HORIZONTAL FILTER
K
H
ERNELS
DOUT
2
12
H
11-0
3
HV
6
V
V
V
V
V
V
1
2
3
5
6
7
Horizontal / Vertical Digital Image Filter
4
H
5
H
6
H
7
rectly because the data delays are cal-
culated assuming that the first 3, 5,
or 7 multipliers are used. Also, the
ALUs in the horizontal filter should
be configured to accept data from the
forward I/D Register path into ALU
Input A and force ALU Input B to 0.
FUNCTIONAL DESCRIPTION
Horizontal Filter
The horizontal filter is designed to
filter a digital image in the horizontal
dimension. This FIR filter can be con-
figured to have as many as 16-taps
when symmetric coefficient sets are
used and 8-taps when asymmetric
coefficient sets are used.
ALUs
The ALUs double the number of filter
taps available, when symmetric coeffi-
cient sets are used, by pre-adding data
values which are then multiplied by
a common coefficient (see Figure 8).
The ALUs can perform two opera-
tions: A+B and B–A. Bit 0 of Con-
figuration Register 0 determines the
ALU operation. A+B is used with
even-symmetric coefficient sets. B–A
is used with odd-symmetric coeffi-
cient sets. Also, either the A or B oper-
and may be set to 0. Bits 1 and 2
of Configuration Register 0 control the
ALU inputs. A+0 or B+0 are used
with asymmetric coefficient sets.
Interleave/Decimation Registers
The Interleave/Decimation Registers
(I/D Registers) feed the ALU inputs.
They allow the device to filter up to
sixteen data sets interleaved into the
same data stream without having to
separate the data sets. The I/D Regis-
ters should be set to a length equal
to the number of data sets interleaved
together. For example, if two data sets
are interleaved together, the I/D Reg-
isters should be set to a length of
two. Bits 1 through 4 of Configuration
Register 1 determine the I/D Register
length.
Video Imaging Products
9/14/2005-LDS.3310-I
LF3310