km4132g271a ETC-unknow, km4132g271a Datasheet - Page 9

• Manufacturer Part Number: km4132g271a
• Description: 128k 32bit Banks Synchronous Graphic
• Manufacturer: ETC-unknow

KM4132G271A
SIMPLIFIED TRUTH TABLE
Note :
Register
Refresh
Bank Active
& Row Addr.
Read &
Column Address
Write &
Column Address
Block Write &
Column Addr.
Burst Stop
Precharge
Clock Suspend or
Active Power Down
Precharge Power Down Mode
DQM
No Operation Command
1. OP Code : Operand Code
2. MRS can be issued only at both banks precharge state.
A
A
Color register exists only one per DQi which both banks share.
So dose Mask Register.
Color or mask is loaded into chip through DQ pin.
SMRS can be issued only if DQ's are idle.
A new command can be issued at the next clock of MRS/SMRS.
0
5
, A
~ A
6
9
: LMR or LCR select. (@SMRS)
COMMAND
: Program keys. (@MRS)
Mode Register Set
Special Mode Register Set
Auto Refresh
Self
Refresh
Write Per Bit Disable
Write Per Bit Enable
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Bank Selection
Both Banks
Entry
Entry
Entry
Exit
Exit
Exit
CKEn-1 CKEn
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
X
H
H
X
X
X
X
X
X
H
H
X
L
L
L
CS
H
H
X
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS CAS
H
H
H
H
H
H
H
H
L
L
X
L
L
X
X
X
V
X
X
X
H
X
H
H
H
H
X
X
H
X
V
X
H
X
L
L
L
L
L
(V=Valid, X=Don't Care, H=Logic High, L=Logic Low)
WE
H
H
X
H
H
H
X
X
H
X
V
X
H
X
L
L
L
L
L
DSF DQM A
H
H
H
X
X
X
X
V
X
X
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
V
X
Rev.0 (August 1997)
CMOS SGRAM
V
V
V
V
V
X
9
OP CODE
Row Address
A
H
H
H
H
L
L
L
L
8
X
X
X
X
X
X
X
Address
Address
Address
Column
Column
Column
A
7
~ A
X
0
4,5,6,9
4,5,6,9
Note
1,2,7
4,5,9
1, 2
4, 5
4, 6
4, 5
4, 5
3
3
3
3
4
7
8