km4132g271a ETC-unknow, km4132g271a Datasheet - Page 30

• Manufacturer Part Number: km4132g271a
• Description: 128k 32bit Banks Synchronous Graphic
• Manufacturer: ETC-unknow

DQ
CLOCK
KM4132G271A
Read & Write Cycle at Same Bank @Burst Length=4
ADDR
DQM
CKE
RAS
CAS
DSF
WE
CS
CL=2
CL=3
A
A
9
8
*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.
0
Row Active
(A-Bank)
Ra
Ra
1
2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] valid output data available after Row
3. Access time from Row address.
4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, & 8)
enters precharge. Last valid output will be Hi-Z after
At Full page bit burst, burst is wrap-around.
2
t
RCD
*Note 3
t
RAC
3
(A-Bank)
*Note 3
t
RAC
Read
Ca0
4
5
Qa0
t
SAC
6
t
RC
t
CC
Qa1
Qa0
t
t
*Note 1
*(
OH
SAC
7
t
Precharge
RCD
(A-Bank)
Qa2
Qa1
t
OH
+ CAS latency - 1) +
*Note 2
8
Qa3
Qa2
9
t
SHZ
HIGH
Qa3
t
SHZ
Row Active
from the clcok.
10
(A-Bank)
Rb
Rb
*Note 4
t
SHZ
t
11
SAC
*Note 4
12
13
(A-Bank)
Write
Cb0
Db0
Db0
14
Db1
Db1
Rev.0 (August 1997)
15
Db2
Db2
CMOS SGRAM
16
Db3
Db3
17
Precharge
(A-Bank)
: Don't care
t
t
18
RDL
RDL
19