km4132g271a ETC-unknow, km4132g271a Datasheet - Page 7

• Manufacturer Part Number: km4132g271a
• Description: 128k 32bit Banks Synchronous Graphic
• Manufacturer: ETC-unknow

KM4132G271A
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Note :
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to new col. address delay
Last data in to row precharge
Block write data-in to PRE command delay
Block write data-in to Active(REF)
command period(Auto precharge)
Last data in to burst stop
Col. address to col. address delay
Block write cycle time
Number of valid output data
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change except block write cycle.
4. This parameter means minimum CAS to CAS delay at block write cycle only.
5. In case of row precharge interrupt, auto precharge and read burst stop.
rounding off to the next higher integer.
Parameter
CAS Latency=3
CAS Latency=2
t
t
t
t
t
t
t
t
t
t
t
t
t
RRD(min)
RCD(min)
RP(min)
RAS(min)
RAS(max)
RC(min)
CDL(min)
RDL(min)
BPL(min)
BAL(min)
BDL(min)
CCD(min)
BWC(min)
Symbol
16
16
24
48
80
16
40
16
-8
Version
100
-10
20
20
26
50
80
20
46
20
1
1
1
1
2
1
-12
24
24
30
60
90
24
54
24
Rev.0 (August 1997)
CMOS SGRAM
Unit
CLK
CLK
CLK
CLK
CLK
ns
ns
ns
ns
us
ns
ns
ns
ns
Note
1, 4
1
1
1
1
1
2
2
2
3
5