km4132g271a ETC-unknow, km4132g271a Datasheet - Page 39

• Manufacturer Part Number: km4132g271a
• Description: 128k 32bit Banks Synchronous Graphic
• Manufacturer: ETC-unknow

CLOCK
KM4132G271A
Write Interrupted by Precharge Command & Write Burst Stop Cycle (@ Full page Only)
ADDR
DQM
CKE
RAS
CAS
DSF
WE
DQ
CS
A
A
9
8
*Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
Row Active
0
(A-Bank)
RAa
RAa
1
2. Data-in at the cycle of burst stop command cannot be written into the corresponding memory cell.
3. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell.
4. Burst stop is valid only at full page burst length.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
It is defined by AC parameter of
It is defined by AC parameter of
DQM at write interrupted by precharge command is needed to ensure
Input data after Row precharge cycle will be masked internally.
2
3
(A-Bank)
*Note 1
Write
CAa
DAa0 DAa1 DAa2 DAa3 DAa4
4
5
6
t
t
BDL
RDL
(=1CLK).
7
(=1CLK).
*Note 2
8
Burst Stop
tBDL
9
HIGH
10
(A-Bank)
Write
*Note 1
DAb0 DAb1 DAb2 DAb3 DAb4
CAb
11
t
RDL
12
of 1CLK.
13
14
Rev.0 (August 1997)
15
DAb5
*Note 3
CMOS SGRAM
16
Precharge
(A-Bank)
t
17
RDL
: Don't care
18
19