s87c751-5a28 NXP Semiconductors, s87c751-5a28 Datasheet - Page 16

• Manufacturer Part Number: s87c751-5a28
• Description: 80c51 8-bit Microcontroller Family 2k/64 Otp/rom, I2c, Low Pin Count
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 4.
Table 5.
I
READ ONLY
This register is read only and reflects the internal status of the I
hardware. IDLE, XSTR, and XSTP reflect the status of the like
named bits in the I2CON register.
XDATA
XACTV
MAKSTR This bit is high while the hardware is effecting a start
MAKSTP This bit is high while the hardware is effecting a stop
XSTR
XSTP
Interrupts
The interrupt structure is a five-source, one-level interrupt system.
Interrupt sources common to the 80C51 are the external interrupts
(INT0, INT1) and the timer/counter interrupt (ET0). The I
(EI2) and Timer I interrupt (ETI) are the other two interrupt sources.
The interrupt sources are listed below in their order of polling
sequence priority.
Upon interrupt or reset the program counter is loaded with specific
values for the appropriate interrupt service routine in program
memory. These values are:
Event
Reset
INT0
Counter/Timer 0
INT1
Timer I
I
1998 May 01
2
2
MSB
C Register I2STA
C
All 0
All 0
Any or all 1
Any or all 1
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I
MASTRQ,
SLAVEN,
MASTER
7
–
IDLE
Transmitter active.
condition.
condition.
This bit is active while the hardware is effecting a
repeated start condition.
This bit is active while the hardware is effecting a
repeated stop condition.
6
The content of the transmitter buffer.
CT1, CT0
Interaction of TIRUN with SLAVEN, MASTRQ, and MASTER
CT1, CT0 Values
Program Memory
10
01
00
11
XDATA
TIRUN
5
Address
0
1
0
1
000
003
00B
013
01B
023
XACTV
4
The I
application wants to ignore the I
The I
applications.
The I
not, so that there is no checking for I
The I
Start and Stop conditions. This is the normal state for I
2
2
2
2
MAKSTR
C interface is disabled. Timer I is cleared and does not run. This is the state assumed after a reset. If an I
C interface is disabled. Timer I operates as a free-running time base. Use this mode only in non-I
C interface is enabled. The 3 low-order bits of Timer I run for min-time generation, but the hi-order bits do
C interface is enabled. Timer I runs during frames on the I
2
3
C, low pin count
Priority
Highest
Lowest
MAKSTP
OSC/12 COUNT
2
7
6
5
4
XSTR
1
2
C interrupt
2
C at certain times, it should write SLAVEN, MASTRQ, and TIRUN all to zero.
XSTP
2
0
C
LSB
2
C being “hung.” This configuration can be used for very slow I
16
OPERATING MODE
The interrupt enable register (IE) is used to individually enable or
disable the five sources. Bit EA in the interrupt enable register can
be used to globally enable or disable all interrupt sources. The
interrupt enable register is described below. All other interrupt details
are based on the 80C51 interrupt architecture.
Interrupt Enable Register
Symbol Position
EI2
ETI
EX1
ET0
EX0
EA
–
–
EA
7
2
C operation.
f
16.8MHz
14.4MHz
12.0MHz
OSC
IE.7
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
9.6MHz
6
X
MAX
2
C, and is cleared by transitions on SCL, and by
X
5
Function
Disables all interrupts. If EA = 0, no interrupt
will be acknowledged. If EA = 1, each interrupt
source is individually enabled or disabled by
setting or clearing its enable bit
Reserved
Reserved
Enables or disables the I
If EI2 = 0, the I
Enables or disables the Timer I overflow
interrupt. If ETI = 0, the Timer I interrupt is
disabled.
Enables or disables external interrupt 1.
If EX1 = 0, external interrupt 1 is disabled.
Enables or disables the Timer 0 overflow
interrupt. If ET0 = 0, theTimer 0 interrupt is
disabled.
Enables or disables external interrupt 0.
If EX0 = 0, external interrupt 0 is disabled.
EI2
4
83C751/87C751
ETI
2
3
C interrupt is disabled
TIMEOUT PERIOD
1023 cycles
1022 cycles
1021 cycles
1020 cycles
EX1
2
2
C interrupt.
Product specification
2
C operation.
ET0
1
2
C
EX0
0
2
C