s87c751-5a28 NXP Semiconductors, s87c751-5a28 Datasheet - Page 15

• Manufacturer Part Number: s87c751-5a28
• Description: 80c51 8-bit Microcontroller Family 2k/64 Otp/rom, I2c, Low Pin Count
• Manufacturer: NXP Semiconductors

Philips Semiconductors
I
RDAT
XDAT
Regarding Software Response Time
Because the 83C751 can run at 16MHz, and because the I
interface is optimized for high-speed operation, it is quite likely that
an I
at a rising edge of SCL) and write I2DAT before SCL has gone low
again. If XDAT were applied directly to SDA, this situation would
produce an I
about this possibility because XDAT is applied to SDA only when
SCL is low.
Conversely, a program that includes an I
a long time to respond to DRDY. Typically, an I
on a flag-polling basis during a message, with interrupts from other
peripheral functions enabled. If an interrupt occurs, it will delay the
response of the I
about this very much either, because the I
SCL low time until the service routine responds. The only constraint
on the response is that it must not exceed the Timer I time-out,
which is at least 765 microseconds.
1998 May 01
2
C Register I2DAT
Read
Write
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I
2
C service routine will sometimes respond to DRDY (which is set
RDAT
XDAT
“Receive DATa” is captured from SDA every rising edge of
SCL. Reading I2DAT also clears DRDY and the Transmit
Active state.
“Xmit Data” sets the data for the next bit. Writing I2DAT
also clears DRDY and sets the Transmit Active state.
7
2
C protocol violation. The programmer need not worry
2
C service routine. The programmer need not worry
X
6
0
5
0
X
4
0
X
2
C, low pin count
2
3
0
X
C service routine may take
2
C hardware stretches the
2
C routine operates
X
2
0
X
1
0
2
C
X
0
0
15
I
SLAVEN Writing a 1 to “SLAVe ENable” enables the slave functions
MASTRQ Writing a 1 to “MASTRQ” requests mastership of the I
CLRTI
TIRUN
CT1,0
Values to be used in the CT1 and CT0 bits are shown in Table 5. To
allow the I
oscillator frequency, compare the actual oscillator rate to the f
max column in the table. The value for CT1 and CT0 is found in the
first line of the table where f
actual frequency.
The table also shows the osc/12 count for various settings of
CT1/CT0. This allows calculation of the actual minimum high and
low times for SCL as follows:
SCL min high/low time (in microseconds) = 12 * count / osc (in MHz)
For instance, at a 16MHz frequency, with CT1/CT0 set to 10, the
minimum SCL high and low times will be 5.25 s.
The table also shows the Timer I timeout period (given in machine
cycles) for each CT1/CT0 combination. The timeout period varies
because of the way in which minimum SCL high and low times are
measured. When the I
at every SCL transition with a value dependent upon CT1/CT0. The
preload value is chosen such that a minimum SCL high or low time
has elapsed when Timer I reaches a count of 008 (the actual value
preloaded into Timer I is 8 minus the osc/12 count).
2
C Register I2CFG
Read
Write
of the I
I
and by an I
SLAVEN
SLAVEN
2
2
If a frame from another master is in progress when this
bit is changed from 0 to 1, action is delayed until a stop
condition is detected. Then, or immediately if a frame is
not in progress, a start condition is sent and DRDY is set
(thus making ATN 1 and generating an I
When a master wishes to release mastership status of
the I
cleared by reset and by an I
Writing a 1 to this bit clears the Timer I interrupt flag. This
bit position always reads as a 0.
Writing a 1 to this bit lets Timer I run; a zero stops and
clears it. Together with SLAVEN, MASTRQ, and
MASTER, this bit determines operational modes as
shown in Table 4.
These two bits are programmed as a function of the OSC
rate, to optimize the MIN HI and LO time of SCL when
this 83C751 is a master on the I
determined by these bits controls both of these
parameters, and also the timing for stop and start
conditions. These bits are cleared to 00 by reset.
C bus to run at the maximum rate for a particular
C hardware is disabled. This bit is cleared to 0 by reset
7
2
C, it writes a 1 to XSTP in I2CON. MASTRQ is
2
C subsystem. If SLAVEN and MASTRQ are 0, the
MASTRQ
MASTRQ
2
C time-out.
2
6
C interface is operating, Timer I is preloaded
OSC
CLRTI
5
0
max is greater than or equal to the
83C751/87C751
TIRUN
TIRUN
2
4
C time-out.
2
C. The time value
3
–
–
Product specification
2
C interrupt).
2
–
–
CT1
CT1
1
OSC
CT0
CT0
2
0
C.