mcimx50 Freescale Semiconductor, Inc, mcimx50 Datasheet - Page 60

• Manufacturer Part Number: mcimx50
• Description: I.mx50 Applications Processors For Consumer Products
• Manufacturer: Freescale Semiconductor, Inc

Electrical Characteristics
4.7.2
Figure
accesses to external memory devices with the timing parameters mentioned previously for specific control
parameters settings.
60
1
2
3
t is axi_clk cycle time. The maximum allowed axi_clk frequency is 133 MHz, whereas the maximum allowed EIM_BCLK
frequency is 66.5 MHz. As a result, if BCD = 0, axi_clk must be
resulting in a EIM_BCLK of 66.5 MHz. When the clock branch to EIM is decreased to 66.5 MHz, other buses are impacted
which are clocked from this source. See the CCM chapter of the MCIMX50 Applications Processor Reference Manual
(MCIMX50RM) for a detailed clock tree description.
EIM_BCLK parameters are being measured from the 50% point that is, high is defined as 50% of signal value and low is
defined as 50% as signal value.
For signal measurements High is defined as 80% of signal value and Low is defined as 20% of signal value.
EIM_ADDR
EIM_BCLK
EIM_DATA
EIM_CSx
EIM_LBA
EIM_EBx
EIM_RW
EIM_OE
19,
Figure
Examples of EIM Accesses
20,
Last Valid Address
Figure
i.MX50 Applications Processors for Consumer Products, Rev. 0
Figure 19. Synchronous Memory Read Access, WSC=1
21,
WE14
WE10
WE12
Figure
WE4
WE6
22,
Figure
23, and
Address v1
≤
66.5 MHz. If BCD = 1, then 133 MHz is allowed for axi_clk,
WE18
Figure 24
D(v1)
give a few examples of basic EIM
Next Address
WE11
WE7
WE15
WE13
WE19
WE5
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