mcimx50 Freescale Semiconductor, Inc, mcimx50 Datasheet - Page 18

• Manufacturer Part Number: mcimx50
• Description: I.mx50 Applications Processors For Consumer Products
• Manufacturer: Freescale Semiconductor, Inc

Modules List
18
POR_B
RESET_IN_B
SSI_EXT1_CLK,
SSI_EXT2_CLK
TEST_MODE
USB_H1_GPANAIO,
USB_OTG_GPANAIO
USB_H1_RREFEXT,
USB_OTG_RREFEXT
USB_H1_VBUS,
USB_OTG_VBUS
VREF
WDOG_B
Signal Name
This POWER-ON RESET input is a cold reset negative logic input that resets all modules and logic
in the IC. The POR_B pin should have an external 68 K pull-up to NVCC_RESET and a 1 μF
capacitor to ground.
Note: The POR_B input must be immediately asserted at power-up and remain asserted until
after the last power rail is at its working voltage.
This warm reset negative logic input resets all modules and logic except for the following:
The SSI_EXT1_CLK and SSI_EXT2_CLK outputs are recommended for generating a clock output
from the i.MX50. Use of the CKO1 and CKO2 clock outputs is not recommended, as the large
number of combinational logic muxes on those signals will impact jitter and duty-cycle.
Note that these two clock outputs do not have dedicated pins: SSI_EXT1_CLK is IOMUX ALT3 on
the OWIRE pin, and SSI_EXT2_CLK is IOMUX ALT3 of the EPITO pin.
TEST_MODE is for Freescale factory use only. This signal is internally connected to an on-chip
pull-down device. The user must either float this signal or tie it to GND.
These signals are reserved for Freescale manufacturing use only. Users should float these
outputs.
These signals determine the reference current for the USB PHY bandgap reference. An external
6.04 kΩ 1% resistor to GND is required. This resistor should be connected through a short (low
impedance connection) and placed away from other noisy regions.
If USB_H1 is not used, the H1 RREFEXT resistor may be eliminated and the pin left floating. If
USB_OTG is not used, the OTG RREFEXT resistor may be eliminated and the pin left floating.
These inputs are used by the i.MX50 to detect the presence and level of USB 5 V. If either VBUS
input pin is connected to an external USB connector, there is a possibility that a fast 5 V edge rate
during a cable attach could trigger the VBUS input ESD protection, which could result in damage
to the i.MX50 silicon. To prevent this, the system should use some circuitry to prevent the 5 V edge
rate from exceeding 5.25 V / 1 μs. Freescale recommends the use of a low pass filter consisting
of 100 Ω resistor in series and a 1 μF capacitor close to the i.MX50 pin. In the case when the USB
interface is connected on an on-board USB device (for example, 3G modem), the corresponding
USB_VBUS pin may be left floating.
This pin is the DRAM MC reference voltage input. For LPDDR2 and DDR2, this pin should be
connected to ½ of NVCC_EMI_DRAM. For mDDR, this pin should be left floating. The user may
generate VREF using a precision external resistor divider. Use a 1 kΩ 0.5% resistor to GND and
a 1 kΩ 0.5% resistor to NVCC_EMI_DRAM. Shunt each resistor with a closely-mounted 0.1 µF
capacitor.
This output can be used to reset the system PMIC when the i.MX50 processor is locked up. This
output is in the NVCC_MISC domain.
i.MX50 Applications Processors for Consumer Products, Rev. 0
• Test logic (JTAG, IOMUXC, DAP)
• SRTC
• Cold reset logic of WDOG—Some WDOG logic is only reset by POR_B. See WDOG chapter in
the MCIMX50 Applications Processor Reference Manual (MCIMX50RM) for details.
Table 5. Special Signal Considerations (continued)
Remarks
Freescale Semiconductor