mcimx50 Freescale Semiconductor, Inc, mcimx50 Datasheet - Page 13

• Manufacturer Part Number: mcimx50
• Description: I.mx50 Applications Processors For Consumer Products
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
128 Kbytes
Mnemonic
GPU2Dv1
96 Kbytes
Controller
IOMUXC
OCOTP
OWIRE
PWM-1
PWM-2
Block
I
I
I
ROM
RAM
KPP
2
2
2
C-1
C-2
C-3
Graphics
Processing
Unit-2D, ver. 1
I
On-chip OTP
controller
IOMUX Control Slave
Keypad Port
One-Wire
Interface
Pulse Width
Modulation
Internal RAM
Boot ROM
2
Block Name
C Interface
i.MX50 Applications Processors for Consumer Products, Rev. 0
Table 4. i.MX50 Digital and Analog Modules (continued)
Display
Peripherals
Connectivity
Peripherals
Security
Peripherals
Connectivity
Peripherals
Slave
Connectivity
Peripherals
Slave
Connectivity
Peripherals
Slave
Connectivity
Peripherals
Internal
Memory
Internal
Memory
Subsystem
The GPU2Dv1 provides hardware acceleration for 2D graphic algorithms with
sufficient processor power to run desk-top quality interactive graphics
applications on displays up to HD1080 resolution.
I
up to 400 kbps are supported.
The on-chip one-time -programmable (OCOTP) ROM serves the functions of
hardware and software capability bits, Freescale operations and unique-ID,
the customer-programmable cryptography key, and storage of various ROM
and general purpose configuration bits.
This module enables flexible I/O multiplexing. Each I/O pad has default as
well as several alternate functions. The alternate functions are software
configurable.
The KPP supports an 8 × 8 external keypad matrix. The KPP features are as
follows:
One-Wire support provided for interfacing with an on-board EEPROM, and
smart battery interfaces, for example, Dallas DS2502.
The pulse-width modulator (PWM) has a 16-bit counter and is optimized to
generate sound from stored sample audio images. It can also generate tones.
The PWM uses 16-bit resolution and a 4 x 16 data FIFO to generate sound.
The On-Chip Memory controller (OCRAM) module, is an interface between
the system’s AXI bus, to the internal (on-chip) SRAM memory module. It is
used for controlling the 128 Kbyte multimedia RAM, through a 64-bit AXI bus.
Supports secure and regular Boot Modes.
The ROM Controller supports ROM Patching.
2
• Open drain design
• Glitch suppression circuit design
• Multiple keys detection
• Standby key press detection
C provides serial interface for controlling peripheral devices. Data rates of
Brief Description
Modules List
13