mcimx50 Freescale Semiconductor, Inc, mcimx50 Datasheet - Page 26

• Manufacturer Part Number: mcimx50
• Description: I.mx50 Applications Processors For Consumer Products
• Manufacturer: Freescale Semiconductor, Inc

Electrical Characteristics
4.2.2
The power-down sequence is recommended to be the opposite of the power-up sequence. In other words,
the same power supply constraints exist while powering off as while powering on.
4.2.3
When the i.MX50 is resuming from STOP mode, there are some special sequencing considerations. The
resume timing is determined by the following internal counters:
If the PMIC_RDY input is used and BYPASS_PMIC_VFUNCTIONAL_READY = 0, the i.MX50 will
wait for STBY_COUNT cycles after PMIC_STBY_REQ negation before checking PMIC_RDY status.
Once the STBY_COUNT has expired AND the PMIC_RDY signal has been asserted, the OSCNT counter
begins and the 24MHz oscillator is powered up. After OSCNT expires the processor will enter RUN mode.
If the PMIC_RDY input is not used, the processor will attempt to start the 24 MHz oscillator after
STBY_COUNT expires. So at a minimum, all the supplies necessary to start up the 24 MHz oscillator need
to be powered before STBY_COUNT expires: NVCC_SRTC,VDD1P2, VDD1P8, VDD2P5, VDD3P0.
After STBY_COUNT expires, the OSCNT counter begins and the 24 MHz oscillator is powered up. After
OSCNT expires the processor will enter RUN mode, so all other supplies need to be at the appropriate
operating levels before OSCNT expires.
4.3
This section includes the DC parameters of the following I/O types:
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1. STBY_COUNT. This register is in the CCM block and may be set to a maximum of 16 x 32 kHz
2. OSCNT. This register is in the CCM block and may be set to a maximum of 256 x 32 kHz cycles,
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cycles, or 500 μsec.
or 8 msec. This counter is intended to give the 24MHz clock time to start up and stabilize.
General Purpose I/O and High-Speed General Purpose I/O (GPIO)
Double Data Rate 2 (DDR2)
Low Power Double Data Rate 2 (LPDDR2)
Low Power Double Data Rate 1(LPDDR1)
Low Voltage I/O (LVIO)
High Voltage I/O (HVIO)
Secure Digital Host Controllers (eSDHCv2 and eSDHCv3)
USB-OTG and USB Host ports
I/O DC Parameters
Power-Down Sequence
Resume Sequence
1) The POR_B input must be immediately asserted at power-up and remain
asserted until after the last power rail is at its working voltage.
2) No power-up sequence dependencies exist between the supplies shown
shaded in gray.
i.MX50 Applications Processors for Consumer Products, Rev. 0
NOTE
Freescale Semiconductor