mc9s08qg8 Freescale Semiconductor, Inc, mc9s08qg8 Datasheet - Page 81

• Manufacturer Part Number: mc9s08qg8
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

6.4.3
This section provides information about the registers associated with the parallel I/O ports.
Refer to tables in
for all parallel I/O. This section refers to registers and control bits only by their names. A Freescale
Semiconductor-provided equate or header file normally is used to translate these names into the
appropriate absolute addresses.
6.4.3.1
6.4.3.2
Freescale Semiconductor
PTBDD[7:0]
PTBD[7:0]
Reset:
Reset:
Field
Field
7:0
7:0
W
W
R
R
PTBDD7
PTBD7
Port B Registers
Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin. For port B
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTBD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
Data Direction for Port B Bits — These read/write bits control the direction of port B pins and what is read for
PTBD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn.
Port B Data (PTBD)
0
Port B Data Direction (PTBDD)
0
7
7
Chapter 4, “Memory Map and Register
PTBDD6
PTBD6
0
0
6
6
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Figure 6-11. Data Direction for Port B (PTBDD)
Table 6-7. PTBDD Register Field Descriptions
Table 6-6. PTBD Register Field Descriptions
Figure 6-10. Port B Data Register (PTBD)
PTBDD5
PTBD5
0
0
5
5
PTBDD4
PTBD4
0
0
4
4
Description
Description
Definition,” for the absolute address assignments
PTBDD3
PTBD3
3
0
3
0
PTBDD2
PTBD2
Chapter 6 Parallel Input/Output Control
0
0
2
2
PTBDD1
PTBD1
0
0
1
1
PTBDD0
PTBD0
0
0
0
0
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