mc9s08qg8 Freescale Semiconductor, Inc, mc9s08qg8 Datasheet - Page 231

• Manufacturer Part Number: mc9s08qg8
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Refer to the direct-page register summary in the
assignments for all TPM registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
16.3.1
TPMSC contains the overflow status flag and control bits that are used to configure the interrupt enable,
TPM configuration, clock source, and prescale divisor. These controls relate to all channels within this
timer module.
Freescale Semiconductor
CLKS[B:A]
CPWMS
Reset
PS[2:0]
•
Field
TOIE
TOF
4:3
2:0
7
6
5
W
R
A 16-bit channel value register (TPMCnVH:TPMCnVL)
Timer Status and Control Register (TPMSC)
TOF
Timer Overflow Flag — This flag is set when the TPM counter changes to 0x0000 after reaching the modulo
value programmed in the TPM counter modulo registers. When the TPM is configured for CPWM, TOF is set
after the counter has reached the value in the modulo register, at the transition to the next lower count value.
Clear TOF by reading the TPM status and control register when TOF is set and then writing a 0 to TOF. If another
TPM overflow occurs before the clearing sequence is complete, the sequence is reset so TOF would remain set
after the clear sequence was completed for the earlier TOF. Reset clears TOF. Writing a 1 to TOF has no effect.
0 TPM counter has not reached modulo value or overflow
1 TPM counter has overflowed
Timer Overflow Interrupt Enable — This read/write bit enables TPM overflow interrupts. If TOIE is set, an
interrupt is generated when TOF equals 1. Reset clears TOIE.
0 TOF interrupts inhibited (use software polling)
1 TOF interrupts enabled
Center-Aligned PWM Select — This read/write bit selects CPWM operating mode. Reset clears this bit so the
TPM operates in up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting
CPWMS reconfigures the TPM to operate in up-/down-counting mode for CPWM functions. Reset clears
CPWMS.
0 All TPM channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the
1 All TPM channels operate in center-aligned PWM mode
Clock Source Select — As shown in
of three clock sources to drive the counter prescaler. The external source and the XCLK are synchronized to the
bus clock by an on-chip synchronization circuit.
Prescale Divisor Select — This 3-bit field selects one of eight divisors for the TPM clock input as shown in
Table
whatever clock source is selected to drive the TPM system.
0
7
MSnB:MSnA control bits in each channel’s status and control register
16-3. This prescaler is located after any clock source synchronization or clock source selection, so it affects
= Unimplemented or Reserved
TOIE
Figure 16-3. Timer Status and Control Register (TPMSC)
0
6
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Table 16-1. TPMSC Register Field Descriptions
CPWMS
0
5
Table
Memory
CLKSB
16-2, this 2-bit field is used to disable the TPM system or select one
0
4
Description
chapter of this data sheet for the absolute address
CLKSA
3
0
PS2
0
2
PS1
Timer/PWM (S08TPMV2)
0
1
PS0
0
0
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