lpc2917 NXP Semiconductors, lpc2917 Datasheet - Page 47

• Manufacturer Part Number: lpc2917
• Description: Arm9 Microcontroller With Can And Lin
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2917_19_1
Preliminary data sheet
8.8.5.1 Overview
8.8.5.2 Description
8.8.5 Reset Generation Unit (RGU)
The key features of the Reset Generation Unit (RGU) are:
The RGU controls all internal resets.
Each reset output is defined as a (combination of) reset input sources including the
external reset input pins and internal power-on reset, see
listed in this table form a sort of cascade to provide the multiple levels of impact that a
reset may have. The combined input sources are logically OR-ed together so that
activating any of the listed reset sources causes the output to go active.
Table 25.
Reset Output
POR_RST
RGU_RST
PCR_RST
COLD_RST
WARM_RST
SCU_RST
CFID_RST
FMC_RST
EMC_RST
SMC_RST
GESS_A2V_RST
PESS_A2V_RST
GPIO_RST
UART_RST
TMR_RST
SPI_RST
IVNSS_A2V_RST
IVNSS_CAN_RST
IVNSS_LIN_RST
MSCSS_A2V_RST
MSCSS_PWM_RST
MSCSS_ADC_RST
MSCSS_TMR_RST
VIC_RST
AHB_RST
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Reset controlled individually per subsystem
Automatic reset stretching and release
Monitor function to trace resets back to source
Register write-protection mechanism to prevent unintentional resets
Reset output configuration
Rev. 1.01 — 15 November 2007
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
Reset Source
power-on reset module
POR_RST, RSTN pin
RGU_RST, WATCHDOG PCR internal; is source for COLD_RST
PCR_RST
COLD_RST
COLD_RST
COLD_RST
COLD_RST
COLD_RST
COLD_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
parts of the device reset when activated
LP_OSC; is source for RGU_RST
RGU internal; is source for PCR_RST
parts with COLD_RST as reset source below
parts with WARM_RST as reset source below
SCU
CFID
embedded Flash-Memory Controller (FMC)
embedded SRAM-Memory Controller
external Static-Memory Controller (SMC)
GeSS AHB-to-VPB bridge
PeSS AHB-to-VPB bridge
all GPIO modules
all UART modules
all Timer modules in PeSS
all SPI modules
IVNSS AHB-to-VPB bridge
all CAN modules including Acceptance filter
all LIN modules
MSCSS AHB to VPB bridge
all PWM modules
all ADC modules
all Timer modules in MSCSS
Vectored Interrupt Controller (VIC)
CPU and AHB Multilayer Bus infrastructure
ARM9 microcontroller with CAN and LIN
Table
25. The first five resets
LPC2917/19
© NXP B.V. 2007. All rights reserved.
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