lpc2917 NXP Semiconductors, lpc2917 Datasheet - Page 13

• Manufacturer Part Number: lpc2917
• Description: Arm9 Microcontroller With Can And Lin
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2917_19_1
Preliminary data sheet
7.2.2 Base clock and branch clock relationship
The next table contains an overview of all the base blocks in the LPC2917/19 and their
derived branch clocks. A short description is given of the hardware parts that are clocked
with the individual branch clocks. In relevant cases more detailed information can be
found in the specific subsystem description. Some branch clocks have special protection
since they clock vital system parts of the device and should (for example) not be switched
off. See
Table 7.
Base clock
BASE_SAFE_CLK
BASE_SYS_CLK
BASE_PCR_CLK
BASE_IVNSS_CLK
Section 8.8.6
Base clock and branch clock overview
Rev. 1.01 — 15 November 2007
for more details of how to control the individual branch clocks.
Branch clock name
CLK_SAFE
CLK_SYS_CPU
CLK_SYS_SYS
CLK_SYS_PCRSS
CLK_SYS_FMC
CLK_SYS_RAM0
CLK_SYS_RAM1
CLK_SYS_SMC
CLK_SYS_GESS
CLK_SYS_VIC
CLK_SYS_PESS
CLK_SYS_GPIO0
CLK_SYS_GPIO1
CLK_SYS_GPIO2
CLK_SYS_GPIO3
CLK_SYS_IVNSS_A
CLK_PCR_SLOW
CLK_IVNSS_VPB
CLK_IVNSS_CANCA
CLK_IVNSS_CANC0
CLK_IVNSS_CANC1
CLK_IVNSS_LIN0
CLK_IVNSS_LIN1
ARM9 microcontroller with CAN and LIN
Parts of the device clocked by
this branch clock
Watchdog Timer
ARM968E-S and TCMs
AHB Bus infrastructure
AHB side of bridge in PCRSS
Flash-Memory Controller
Embedded SRAM Controller 0
(32 KByte)
Embedded SRAM Controller 1
(16 KByte)
External Static-Memory
Controller
General Subsystem
Vectored Interrupt Controller
Peripheral Subsystem
GPIO bank 0
GPIO bank 1
GPIO bank 2
GPIO bank 3
AHB side of bridge of IVNSS
PCRSS, CGU, RGU and PMU
logic clock
VPB side of the IVNSS
CAN controller Acceptance Filter
CAN channel 0
CAN channel 1
LIN channel 0
LIN channel 1
LPC2917/19
© NXP B.V. 2007. All rights reserved.
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