lpc2106fhn48/00 NXP Semiconductors, lpc2106fhn48/00 Datasheet - Page 22

• Manufacturer Part Number: lpc2106fhn48/00
• Description: Single-chip 32-bit Microcontrollers; 128 Kb Isp/iap Flash With 64 Kb/32 Kb/16 Kb Ram
• Manufacturer: NXP Semiconductors

Philips Semiconductors
LPC2104_2105_2106_6
Product data sheet
6.17.3 Reset and wake-up timer
6.17.4 External interrupt inputs
6.17.5 Memory mapping control
6.17.6 Power control
by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,
it is insured that the PLL output has a 50 % duty cycle.The PLL is turned off and bypassed
following a chip Reset and may be enabled by software. The program must configure and
activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The
PLL settling time is 100 s.
Reset has two sources on the LPC2104/2105/2106: the RESET pin and Watchdog Reset.
The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of
chip Reset by any source starts the wake-up timer (see wake-up timer description below),
causing the internal chip reset to remain asserted until the external Reset is de-asserted,
the oscillator is running, a fixed number of clocks have passed, and the on-chip flash
controller has completed its initialization.
When the internal Reset is removed, the processor begins executing at address 0, which
is the Reset vector. At that point, all of the processor and peripheral registers have been
initialized to predetermined values.
The wake-up timer ensures that the oscillator and other analog functions required for chip
operation are fully functional before the processor is allowed to execute instructions. This
is important at power on, all types of Reset, and whenever any of the aforementioned
functions are turned off for any reason. Since the oscillator and other functions are turned
off during Power-down mode, any wake-up of the processor from Power-down mode
makes use of the wake-up timer.
The wake-up timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of V
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.
The LPC2104/2105/2106 include three External Interrupt Inputs as selectable pin
functions. The External Interrupt Inputs can optionally be used to wake up the processor
from Power-down mode.
The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip
flash memory, or to the on-chip static RAM. This allows code running in different memory
spaces to have control of the interrupts.
The LPC2104/2105/2106 support two reduced power modes: Idle mode and Power-down
mode. In Idle mode, execution of instructions is suspended until either a Reset or interrupt
occurs. Peripheral functions continue operation during Idle mode and may generate
interrupts to cause the processor to resume execution. Idle mode eliminates power used
by the processor itself, memory systems and related controllers, and internal buses.
Rev. 06 — 25 July 2006
DD
ramp (in the case of power on), the type of crystal
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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