lpc2106fhn48/00 NXP Semiconductors, lpc2106fhn48/00 Datasheet - Page 18

• Manufacturer Part Number: lpc2106fhn48/00
• Description: Single-chip 32-bit Microcontrollers; 128 Kb Isp/iap Flash With 64 Kb/32 Kb/16 Kb Ram
• Manufacturer: NXP Semiconductors

Philips Semiconductors
LPC2104_2105_2106_6
Product data sheet
6.10.1 Features
6.11.1 Features
6.11 I
6.12 SPI serial I/O controller
I
and a serial data line (SDA). Each device is recognized by a unique address and can
operate as either a receiver-only device (e.g. an LCD driver or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. I
controlled by more than one bus master connected to it.
The I
I
The SPI is a full duplex serial interface, designed to be able to handle multiple masters
and slaves connected to a given bus. Only a single master and a single slave can
communicate on the interface during a given data transfer. During a data transfer the
master always sends a byte of data to the slave, and the slave always sends a byte of data
to the master.
2
2
2
•
•
•
•
•
C is a bidirectional bus for inter-IC control using only two wires: a serial clock line (SCL),
C-bus).
•
•
•
•
•
•
•
•
•
C-bus serial I/O controller
16 byte Receive and Transmit FIFOs
Register locations conform to 16C550 industry standard
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B
Built-in baud rate generator
Standard modem interface signals included on UART 1.
Standard I
Easy to configure as Master, Slave, or Master/Slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
2
C-bus implemented in LPC2104/2105/2106 supports bit rate up to 400 kbit/s (Fast
2
C-bus may be used for test and diagnostic purposes.
2
C compliant bus interface.
Rev. 06 — 25 July 2006
2
LPC2104/2105/2106
C is a multi-master bus, it can be
Single-chip 32-bit microcontrollers
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
18 of 35