pic32mx320f032h Microchip Technology Inc., pic32mx320f032h Datasheet - Page 73

• Manufacturer Part Number: pic32mx320f032h
• Description: 64/100-pin General Purpose And Usb 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

12.0
General purpose I/O pins are the simplest of peripher-
als. They allow the PIC
other devices. To add flexibility and functionality, some
pins are multiplexed with alternate function(s).
FIGURE 12-1:
© 2009 Microchip Technology Inc.
Note:
Legend: R = Peripheral input buffer types may vary. Refer to Table 1-1 for more information.
Note:
PIO Module
WR PORT
WR TRIS
RD PORT
WR ODC
Peripheral Input
Data Bus
RD ODC
RD TRIS
I/O PORTS
SYS
WR LAT
SYS
RD LAT
Sleep
reference source. Refer to the “PIC32MX
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
Family Reference Manual” Section 12. “I/O
Ports” (DS61120) for a detailed description
of this peripheral.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The
actual structure for any specific port/peripheral combination may be different than it is shown here.
CLK
CLK
BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE
®
MCU to monitor and control
Peripheral Input Buffer
Peripheral Output Enable
Peripheral Module Enable
Peripheral Output Data
Peripheral Module
D
D
D
CK
CK
CK
EN Q
EN Q
EN Q
R
Q
Q
Q
Preliminary
ODC
TRIS
LAT
0
1
Q
Q
Output Multiplexers
These functions depend on which peripheral features
are on the device. In general, when a peripheral is func-
tioning, that pin may not be used as a general purpose
I/O pin.
Following are some of the key features of this module:
• Individual output pin open-drain enable/disable
• Individual input pin weak pull-up enable/disable
• Monitor selective inputs and generate interrupt
• Operation during CPU Sleep and Idle modes
• Fast bit manipulation using CLR, SET and INV
Figure 12-1 shows a block diagram of a typical
multiplexed I/O port.
when change in pin state is detected
registers
CK
Synchronization
D
1
0
1
0
PIC32MX3XX/4XX
Q
Q
CK
D
0
1
DS61143F - page 71
IO Cell
IO Pin