pic32mx320f032h Microchip Technology Inc., pic32mx320f032h Datasheet - Page 69

• Manufacturer Part Number: pic32mx320f032h
• Description: 64/100-pin General Purpose And Usb 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

10.0
The PIC32MX Direct Memory Access (DMA) controller
is a bus master module useful for data transfers
between different devices without CPU intervention.
The source and destination of a DMA transfer can be
any of the memory mapped modules existent in the
PIC32MX (such as Peripheral Bus (PBUS) devices:
SPI, UART, I
Following are some of the key features of the DMA
controller module:
• Four Identical Channels, each featuring:
• Automatic Word-Size Detection:
FIGURE 10-1:
© 2009 Microchip Technology Inc.
Note:
- Auto-Increment Source and Destination
- Source and Destination Pointers
- Memory to Memory and Memory to
- Transfer Granularity, down to byte level
- Bytes need not be word-aligned at source
INT Controller
Peripheral Bus
Address Registers
Peripheral Transfers
and destination
DIRECT MEMORY ACCESS
(DMA) CONTROLLER
reference source. Refer to the “PIC32MX
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive
Family Reference Manual” Section 31.
“Direct Memory Access (DMA) Control-
ler” (DS61117) for a detailed description of
this peripheral.
The manual is available from the Microchip
web site (www.Microchip.com/PIC32).
2
C™, etc.) or memory itself.
Address Decoder
Global Control
DMA BLOCK DIAGRAM
(DMACON)
System IRQ
Channel n Control
Channel 0 Control
Channel 1 Control
Preliminary
• Fixed Priority Channel Arbitration
• Flexible DMA Channel Operating Modes:
• Flexible DMA Requests:
• Multiple DMA Channel Status Interrupts:
• DMA Debug Support Features:
• CRC Generation Module:
Channel Priority
- Manual (software) or automatic (interrupt)
- One-Shot or Auto-Repeat Block Transfer
- Channel-to-channel chaining
- A DMA request can be selected from any of
- Each channel can select any (appropriate)
- A DMA transfer abort can be selected from
- Pattern (data) match transfer termination
- DMA channel block transfer complete
- Source empty or half empty
- Destination full or half-full
- DMA transfer aborted due to an external
- Invalid DMA address generated
- Most recent address accessed by a DMA
- Most recent DMA channel to transfer data
- CRC module can be assigned to any of the
- CRC module is highly configurable
Arbitration
I
I
I
I
DMA requests
modes
the peripheral interrupt sources
observable interrupt as its DMA request
source
any of the peripheral interrupt sources
event
channel
available channels
0
1
2
n
PIC32MX3XX/4XX
Y
Bus Interface
Device Bus + Bus Arbitration
DS61143F-page 67