pic32mx320f032h Microchip Technology Inc., pic32mx320f032h Datasheet - Page 110

• Manufacturer Part Number: pic32mx320f032h
• Description: 64/100-pin General Purpose And Usb 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

PIC32MX3XX/4XX
26.2
This section describes the operation of the WDT and
Power-Up Timer of the PIC32MX3XX/4XX.
The WDT, when enabled, operates from the internal
Low-Power Oscillator (LPRC) clock source and can be
used to detect system software malfunctions by reset-
ting the device if the WDT is not cleared periodically in
software. Various WDT time-out periods can be
selected using the WDT postscaler. The WDT can also
be used to wake the device from Sleep or Idle mode.
FIGURE 26-1:
26.3
All PIC32MX3XX/4XX device’s core and digital logic
are designed to operate at a nominal 1.8V. To simplify
system
PIC32MX3XX/4XX incorporate an on-chip regulator
providing the required core logic voltage from V
The internal 1.8V regulator is controlled by the
ENVREG pin. Tying this pin to V
lator, which in turn provides power to the core. A low
ESR capacitor (such as tantalum) must be connected
to the V
maintain the stability of the regulator. The recom-
mended value for the filer capacitor is provided in
Section 28.1 “DC Characteristics” .
DS61143F-page 108
Note:
WDTCLR =
WDT Enable
DDCORE
Watchdog Timer (WDT)
On-Chip Voltage Regulator
PWRT Enable
designs,
Oscillator
It is important that the low ESR capacitor
is placed as close as possible to the
V
WDT Enable
LPRC
DDCORE
Wake
/V
1
CAP
/V
WATCHDOG AND POWER-UP TIMER BLOCK DIAGRAM
pin (Figure 26-2). This helps to
CAP
most
pin.
DD
devices
enables the regu-
WDT Counter Reset
in
DD
Clock
.
Preliminary
the
25-bit Counter
FWDTPS<4:0>(DEVCFG1<20:16>)
The following are some of the key features of the WDT
module:
• Configuration or software controlled
• User-configurable time-out period
• Can wake the device from Sleep or Idle
Tying the ENVREG pin to V
this case, separate power for the core logic at a nomi-
nal 1.8V must be supplied to the device on the
V
Alternately, the V
tied together to operate at a lower nominal voltage.
Refer to Figure 26-2 for possible configurations.
26.3.1
When the voltage regulator is enabled, it takes fixed
delay for it to generate output. During this time, desig-
nated as T
every time the device resumes operation after any
power-down, including Sleep mode.
If the regulator is disabled, a separate Power-Up Timer
(PWRT) is automatically enabled. The PWRT adds a
fixed delay of T
Section 28.0 “Electrical Characteristics” for more
information on T
1:64 Output
DDCORE
25
1
/V
PU
CAP
Decoder
ON-CHIP REGULATOR AND POR
, code execution is disabled. T
pin.
PU AND
PWRT Enable
DDCORE
PWRT
Power Save
T
© 2009 Microchip Technology Inc.
PWRT
/V
0
1
SS
at device start-up. See
CAP
disables the regulator. In
.
and V
Control
PWRT
Device Reset
NMI (Wake-up)
LPRC
DD
pins can be
PU
is applied