pic32mx320f032h Microchip Technology Inc., pic32mx320f032h Datasheet - Page 50

• Manufacturer Part Number: pic32mx320f032h
• Description: 64/100-pin General Purpose And Usb 32-bit Flash Microcontrollers
• Manufacturer: Microchip Technology Inc.

TABLE 4-17:
TABLE 4-18:
Legend:
Note
BF88_61C0
Legend:
Note
BF88_6130
BF88_6140
BF88_6150
BF88_6160
BF88_6170
BF88_6180
BF88_6190
BF88_61A0
BF88_61B0
Virtual
Virtual
Addr
Addr
SFR
SFR
1:
2:
3:
4:
5:
6:
7:
8:
9:
10:
11:
1:
2:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TRISA, PORTA, LATA and ODCA registers are not implemented on 64-pin devices, and read as ‘0’.
JTAG program/debug port is multiplexed with port pins RA0, RA1, RA4 and RA5 on 100-pin devices. At power-on-reset, these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the
user’s application code must clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user’s application code must maintain JTAGEN bit = 1.
On specific 100-pin devices, the instruction TRACE port is multiplexed with PORTA pins RA6, RA7; PORTG pins RG12, RG13 and RG14. At Power-on Reset, these pins are general purpose I/O pins. To maintain
these pins as general purpose I/O pins, the user’s application code must maintain TROEN (DDPCON<2>) bit = 0. To use these pins as instruction TRACE pins, TROEN must be set = 1.
JTAG program/debug port is multiplexed with port pins RB10, RB11, RB12 and RB13 on 64-pin devices. At power-on-reset, these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the
user’s application code must clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user’s application code must maintain JTAGEN bit = 1.
Port Pin RB3 is not available as a general purpose I/O pin when the USB module is enabled.
Not implemented on 64-pin devices. Read as ‘0’.
Not implemented on 64-pin USB devices. Read as ‘0’.
Not implemented on 100-pin USB devices. Read as ‘0’.
Not available as a general purpose I/O pin when USB module is enabled.
Not available as a general purpose I/O pin when USB module is enabled. Input only when the USB module is disabled.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more infor-
mation.
CNCON
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
CNEN and CNPUE bit(s) are not implemented on 64-pin devices, and read as ‘0’.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more infor-
mation.
PORTG
PORTF
Name
TRISG
ODCG
Name
ODCE
TRISF
ODCF
LATG
LATF
SFR
SFR
PORT A-G REGISTERS MAP
CHANGE NOTICE AND PULL-UP REGISTERS MAP
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0 TRISG15
15:0
15:0 LATG15
15:0 ODCG15
15:0
RG15
31/15
31/15
Bits
Bits
ON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(6)
(6)
(6)
(6)
TRISG14
ODCG14
LATG14
RG14
30/14
30/14
Bits
Bits
FRZ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(6)
(6)
(6)
(6)
TRISF13
ODCF13
TRISG13
ODCG13
LATG13
LATF13
RF13
RG13
29/13
29/13
SIDL
Bits
Bits
—
—
—
—
—
—
—
—
—
—
—
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
TRISG12
ODCG12
TRISF12
ODCF12
LATG12
LATF12
(11)
RG12
RF12
28/12
28/12
Bits
Bits
—
—
—
—
—
—
—
—
—
—
—
—
(CONTINUED)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
27/11
27/11
Bits
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
26/10
26/10
Bits
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ODCE9
TRISG9
ODCG9
(2)
LATG9
25/9
RG9
25/9
Bits
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(6)
ODCE8
TRISF8
ODCF8
LATF8
TRISG8
ODCG8
LATG8
RF8
Bits
24/8
RG8
Bits
24/8
—
—
—
—
—
—
—
—
—
—
—
(6)
(6)
(6)
(6)
(6)
TRISF7
ODCF7
LATF7
RF7
TRISG7
ODCG7
LATG7
Bits
23/7
RG7
Bits
23/7
—
—
—
—
—
—
—
—
—
—
—
(6,8)
(6,8)
(6,8)
(6,8)
TRISF6
ODCF6
LATF6
TRISG6
RF6
ODCG6
LATG6
Bits
22/6
RG6
Bits
22/6
—
—
—
—
—
—
—
—
—
—
—
(7,8)
(7,8)
(7,8)
(7,8)
TRISF5
ODCF5
LATF5
Bits
21/5
RF5
Bits
21/5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISF4
ODCF4
LATF4
20/4
20/4
Bits
RF4
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ODCE<7:0>
TRISG3
ODCG3
TRISF3
ODCF3
RG3
LATG3
RF3
LATF3
19/3
19/3
Bits
Bits
—
—
—
—
—
—
—
—
—
—
—
(10)
(9)
TRISF2
ODCF2
LATF2
TRISG2
RG2
ODCG2
LATG2
RF2
18/2
18/2
Bits
Bits
—
—
—
—
—
—
—
—
—
—
—
(10)
(7)
(7)
(7)
(7)
TRISG1
ODCG1
LATG1
TRISF1
ODCF1
RG1
LATF1
Bits
17/1
Bits
17/1
RF1
—
—
—
—
—
—
—
—
—
—
—
(6)
(6)
(6)
(6)
TRISG0
ODCG0
LATG0
TRISF0
ODCF0
LATF0
RG0
Bits
16/0
Bits
16/0
RF0
—
—
—
—
—
—
—
—
—
—
—
(6)
(6)
(6)
(6)