atmega161-4pi ATMEL Corporation, atmega161-4pi Datasheet - Page 78

• Manufacturer Part Number: atmega161-4pi
• Description: 8-bit Microcontroller With 16k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

UART0 and UART1 High Byte
Baud Rate Register UBRRHI
UART0 Baud Rate Register
Low Byte – UBRR0
UART1 Baud Rate Register
Low Byte – UBRR1
Double-speed
Transmission
78
ATmega161(L)
The UART Baud Register is a 12-bit register. The four most significant bits are located in
a separate register, UBRRHI. Note that both UART0 and UART1 share this register. Bit
7 to bit 4 of UBRRHI contain the four most significant bits of the UART1 Baud Register.
Bit 3 to bit 0 contain the four most significant bits of the UART0 Baud Register.
UBRRn stores the eight least significant bits of the UART Baud Rate Register.
The ATmega161 provides a separate UART mode that allows the user to double the
communication speed. By setting the U2X bit in UART Control and Status Register
UCSRnA, the UART speed will be doubled. The data reception will differ slightly from
Normal mode. Since the speed is doubled, the Receiver front-end logic samples the sig-
nals on RXDn pin at a frequency 8 times the baud rate. While the line is idle, one single
sample of logical “0” will be interpreted as the falling edge of a start bit, and the start bit
detection sequence is initiated. Let sample 1 denote the first zero-sample. Following the
1-to-0 transition, the Receiver samples the RXDn pin at samples 4, 5 and 6. If two or
more of these three samples are found to be logical “1”s, the start bit is rejected as a
noise spike and the Receiver starts looking for the next 1-to-0 transition.
If, however, a valid start bit is detected, sampling of the data bits following the start bit is
performed. These bits are also sampled at samples 4, 5 and 6. The logical value found
in at least two of the three samples is taken as the bit value. All bits are shifted into the
Transmitter Shift Register as they are sampled. Sampling of an incoming character is
shown in Figure 47.
Figure 47. Sampling Received Data when the Transmission Speed is Doubled
Bit
$20 ($40)
Read/Write
Initial Value
Bit
$09 ($29)
Read/Write
Initial Value
Bit
$00 ($20)
Read/Write
Initial Value
SAMPLING
RECEIVER
RXD
START BIT
MSB1
MSB
MSB
R/W
R/W
R/W
7
0
7
0
7
0
D0
R/W
R/W
R/W
6
0
6
0
6
0
D1
R/W
R/W
R/W
5
0
5
0
5
0
D2
LSB1
R/W
R/W
R/W
4
0
4
0
4
0
D3
MSB0
R/W
R/W
R/W
3
0
3
0
3
0
D4
R/W
R/W
R/W
2
0
2
0
2
0
D5
R/W
R/W
R/W
1
0
1
0
1
0
D6
LSB0
R/W
LSB
R/W
LSB
R/W
0
0
D7
1228D–AVR–02/07
0
0
0
0
STOP BIT
UBRRHI
UBRR0
UBRR1