atmega161-4pi ATMEL Corporation, atmega161-4pi Datasheet - Page 55

• Manufacturer Part Number: atmega161-4pi
• Description: 8-bit Microcontroller With 16k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

Timer/Counter1 in PWM Mode
1228D–AVR–02/07
The Input Capture Register is a 16-bit read-only register.
When the rising or falling edge (according to the Input Capture edge setting, ICES1) of
the signal at the Input Capture pin (ICP) is detected, the current value of the
Timer/Counter1 Register (TCNT1) is transferred to the Input Capture Register (ICR1). In
the same cycle, the Input Capture Flag (ICF1) is set (one).
Since the Input Capture Register (ICR1) is a 16-bit register, a temporary register
(TEMP) is used when ICR1 is read to ensure that both bytes are read simultaneously.
When the CPU reads the Low byte ICR1L, the data is sent to the CPU and the data of
the High byte ICR1H is placed in the TEMP Register. When the CPU reads the data in
the High byte ICR1H, the CPU receives the data in the TEMP Register. Consequently,
the Low byte ICR1L must be accessed first for a full 16-bit register read operation.
The TEMP Register is also used when accessing TCNT1, OCR1A and OCR1B. If the
main program and interrupt routines perform access to registers using TEMP, interrupts
must be disabled during access from the main program and interrupt routine.
When the PWM mode is selected, Timer/Counter1 and the Output Compare Register1A
(OCR1A) and the Output Compare Register1B (OCR1B) form a dual 8-, 9-, or 10-bit,
free-running, glitch-free, and phase-correct PWM with outputs on the PD5(OC1A) and
PE2(OC1B) pins. In this mode the Timer/Counter1 acts as an up/down counter, count-
ing up from $0000 to TOP (see Table 17), where it turns and counts down again to zero
before the cycle is repeated. When the counter value matches the contents of the 8, 9,
or 10 least significant bits (depends of the resolution) of OCR1A or OCR1B, the
PD5(OC1A)/PE2(OC1B) pins are set or cleared according to the settings of the
COM1A1/COM1A0 or COM1B1/COM1B0 bits in the Timer/Counter1 Control Register
(TCCR1A). Refer to Table 18 for details.
Alternatively, the Timer/Counter1 can be configured to a PWM that operates at twice the
speed as in the mode described above. Then the Timer/Counter1 and the Output Com-
pare Register1A (OCR1A) and the Output Compare Register1B (OCR1B) form a dual
8-, 9- or 10-bit, free-running and glitch-free PWM with outputs on the PD5(OC1A) and
PE2(OC1B) pins.
Table 17. Timer TOP Values and PWM Frequency
As shown in Table 17, the PWM operates at either 8-, 9-, or 10-bit resolution. Note the
unused bits in OCR1A, OCR1B and TCNT1 will automatically be written to zero by hard-
ware, i.e., bits 9 to 15 will be set to zero in OCR1A, OCR1B and TCNT1 if the 9-bit PWM
resolution is selected. This makes it possible for the user to perform read-modify-write
operations in any of the three resolution modes and the unused bits will be treated as
don’t care.
CTC1
0
0
0
1
1
1
PWM11
0
1
1
0
1
1
PWM10
1
0
1
1
0
1
PWM Resolution
10-bit
10-bit
8-bit
9-bit
8-bit
9-bit
Timer TOP Value
$03FF (1023)
$03FF (1023)
$00FF (255)
$01FF (511)
$00FF (255)
$01FF (511)
ATmega161(L)
Frequency
f
f
f
f
TCK1
TCK1
f
f
TCK1
TCK1
TCK1
TCK1
/1022
/2046
/1024
/510
/256
/512
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