atmega161-4pi ATMEL Corporation, atmega161-4pi Datasheet - Page 44

• Manufacturer Part Number: atmega161-4pi
• Description: 8-bit Microcontroller With 16k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

Timer Counter0 – TCNT0
Timer/Counter2 – TCNT2
Timer/Counter0 Output
Compare Register – OCR0
Timer/Counter2 Output
Compare Register – OCR2
Timer/Counters 0 and 2 in
PWM Mode
44
ATmega161(L)
These 8-bit registers contain the value of the Timer/Counters.
Both Timer/Counters are realized as up or up/down (in PWM mode) counters with read
and write access. If the Timer/Counter is written to and a clock source is selected, it con-
tinues counting in the timer clock cycle following the write operation.
The Output Compare Registers are 8-bit read/write registers. The Timer/Counter Output
Compare Registers contain the data to be continuously compared with the
Timer/Counter. Actions on compare matches are specified in TCCR0 and TCCR2. A
software write to the Timer/Counter Register blocks compare matches in the next
Timer/Counter clock cycle. This prevents immediate interrupts when initializing the
Timer/Counter.
A compare match will set the Compare Interrupt Flag in the CPU clock cycle following
the compare event.
When PWM mode is selected, the Timer/Counter either wraps (overflows) when it
reaches $FF or it acts as an up/down counter.
If the up/down mode is selected, the Timer/Counter and the Output Compare Registers
(OCR0 or OCR2) form an 8-bit, free-running, glitch-free and phase-correct PWM with
outputs on the PB0(OC0/PWM0) or PB1(OC2/PWM2) pin.
If the Overflow mode is selected, the Timer/Counter and the Output Compare Registers
(OCR0 or OCR2) form an 8-bit, free-running and glitch-free PWM, operating with twice
the speed of the up/down counting mode.
Bit
$32 ($52)
Read/Write
Initial Value
Bit
$23 ($43)
Read/Write
Initial Value
Bit
$31 ($51)
Read/Write
Initial Value
Bit
$22 ($42)
Read/Write
Initial Value
MSB
MSB
R/W
MSB
R/W
R/W
MSB
R/W
7
0
7
0
7
0
7
0
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
R/W
R/W
R/W
3
0
R/W
3
0
3
0
3
0
R/W
R/W
2
0
R/W
R/W
2
0
2
0
2
0
R/W
R/W
1
0
R/W
R/W
1
0
1
0
1
0
LSB
R/W
LSB
R/W
0
0
LSB
R/W
LSB
R/W
0
0
1228D–AVR–02/07
0
0
0
0
TCNT0
TCNT2
OCR0
OCR2