a8290 Allegro MicroSystems, Inc., a8290 Datasheet - Page 9

• Manufacturer Part Number: a8290
• Description: A8290 Single Lnb Supply And Control Voltage Regulator
• Manufacturer: Allegro MicroSystems, Inc.

A8290
EXTM pin (external modulation), in conjunction with the I
control bits: TMODE (tone modulation) and TGATE (tone gate),
provide the necessary control. The TMODE bit controls whether
the tone source is either internal or external (via the EXTM pin).
Both the EXTM pin and TGATE bit determine the 22 kHz con-
trol, whether gated or clocked.
that when using option 4, when EXTM stops clocking, the LNB
volts park at the LNB voltage, either plus or minus half the tone
signal amplitude, depending on the state of EXTM. For example,
if the EXTM is held low, the LNB dc voltage is the LNB pro-
grammed voltage minus 325 mV (typical).
Figure 2. Options for tone generation
Option 1 – Use internal tone, gated by the TGATE bit.
Option 2 – Use internal tone, gated by the EXTM pin.
Option 3 – Use external tone, gated by the TGATE bit.
Option 4 – Use external tone.
Four options for tone generation are shown in figure 2. Note
TMODE
TMODE
TMODE
TMODE
TGATE
Tone
(LNB Ref)
EXTM
EXTM
TGATE
Tone
(LNB Ref)
EXTM
TGATE
Tone
(LNB Ref)
EXTM
TGATE
Tone
(LNB Ref)
Single LNB Supply and Control Voltage Regulator
LNB (V)
LNB (V)
LNB (V)
LNB (V)
2
C™
TDET is set in the status register. When the internal tone is used
(options 1 or 2), the minimum tone detect amplitude is 400 mV,
and when an external tone is used (options 3 or 4), the minimum
tone detection amplitude is 300 mV.
DiSEqC™ Bypass MOSFET
A pair of N-channel MOSFETs are connected in parallel (source
to drain and drain to source) to provide a low source output
impedance during tone transmission.
tive low) or by setting the BFC2 bit to 1 in the Control register.
When the BFC pin is used instead of I
latched; a logic high or low turns the FET off or on. When the
I
but the pull up resistor R5 must be present.
I
This is a serial interface that uses two bus lines, SCL and SDA,
to access the internal Control and Status registers of the A8290.
Data is exchanged between a microcontroller (master) and the
A8290 (slave). The clock input to SCL is generated by the master,
while SDA functions as either an input or an open drain output,
depending on the direction of the data.
Timing Considerations
The control sequence of the communication through the I
compatible interface is composed of several steps in sequence:
1. Start Condition. Defined by a negative edge on the SDA line,
2. Address Cycle. 7 bits of address, plus 1 bit to indicate read (1)
3. Data Cycles.
4. Stop Condition. Defined by a positive edge on the SDA line,
2
2
C™-compatible interface is used, the BFC pin is not connected,
C™-Compatible Interface
while SCL is high.
or write (0), and an acknowledge bit. The first five bits of the
address are fixed as: 00010. The four optional addresses, de-
fined by the remaining two bits, are selected by the ADD input.
The address is transmitted MSB first.
Write – 6 bits of data and 2 bits for addressing four internal
control registers, followed by an acknowledge bit. See Control
Register section for more information.
Read – Two status registers, where register 1 is read first,
followed by register 2, then register 1, and so on. At the start
of any read sequence, register 1 is always read first. Data is
transmitted MSB first.
while SCL is high. Except to indicate a Start or Stop condi-
tion, SDA must be stable while the clock is high. SDA can
only be changed while SCL is low. It is possible for the Start or
Stop condition to occur at any time during a data transfer. The
A8290 always responds by resetting the data transfer sequence.
With any of the four options, when a tone signal is generated,
The MOSFETs are enabled either via the BFC input pin (ac-
115 Northeast Cutoff, Box 15036
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com
2
C™ control, it is not
2
C™-
9