a8290 Allegro MicroSystems, Inc., a8290 Datasheet - Page 15
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a8290
Manufacturer Part Number
a8290
Description
A8290 Single Lnb Supply And Control Voltage Regulator
Manufacturer
Allegro MicroSystems, Inc.
Datasheet
1.A8290.pdf
(19 pages)
A8290
Status Registers
The main fault conditions: overcurrent (OCP), under voltage
(VUV) and overtemperature (TSD), are all indicated by setting
the relevant bits in the Status registers. In all fault cases, once the
bit is set, it remains latched until the A8290 is read by the I
master, assuming the fault has been resolved.
able bit, DIS. The DIS bit is set when either a fault occurs or if
the LNB is disabled intentionally. This bit is latched, and is reset
when the LNB is commanded on again. The power not good
(PNG), tone detect (TDET), and cable disconnected (CAD) flags
are the only bits which may be reset without an I
quence. Table 5 summarizes the condition of each bit when set and
how it is reset.
The current status of the LNB output is indicated by the dis-
As the A8290 has a comprehensive set of status reporting bits,
Table 5. Status Register Bit Setting
(I
2
Status Bit
C™-Compatible Read Register)
TDET
CAD
OCP
PNG
TSD
VUV
DIS
Single LNB Supply and Control Voltage Regulator
Cable disconnected
LNB disabled, either intentionally or
due to fault
Overcurrent
Power not good
Tone detect
Thermal shutdown
Undervoltage
2
C™ read se-
Function
2
C™
it is necessary to have two Status registers. When performing a
multiple read function, register 1 is read followed by register 2,
then register 1 again and so on. Whenever a new read function is
performed, register 1 is always read first.
to detect the fault by reading the Status registers, then rereading
the Status registers until the status bit is reset indicating the fault
condition is reset. The fault may be detected either by continuously
polling, by responding to an interrupt request (IRQ), or by detect-
ing a fault condition externally and performing a diagnostic poll of
all slave devices. Note that the fully-operational condition of the
Status registers is all 0s, to simplify checking of the Status bit.
The normal sequence of the master in a fault condition will be
Non-latched
Non-latched
Non-latched
Latched
Latched
Latched
Latched
Set
Cable disconnect test off or
cable connected
LNB enabled and no fault
I
LNB volts in range
Tone removed
I
I
2
2
2
C™ read and fault removed
C™ read and fault removed
C™ read and fault removed
115 Northeast Cutoff, Box 15036
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Condition
Reset
15