a8290 Allegro MicroSystems, Inc., a8290 Datasheet - Page 10

• Manufacturer Part Number: a8290
• Description: A8290 Single Lnb Supply And Control Voltage Regulator
• Manufacturer: Allegro MicroSystems, Inc.

A8290
tion. If the Read/Write bit is high, the master reads the contents of
register 1, followed by register 2 if a further read is performed. If
the Read/Write bit is low, the master writes data to one of the two
Control registers. Note that multiple writes are not permitted. All
write operations must be preceded with the address.
ter to determine if the slave device is responding to its address
and data, and it is used by the slave when the master is reading
data back from the slave. When the A8290 decodes the 7-bit ad-
dress field as a valid address, it responds by pulling SDA low
during the ninth clock cycle.
low during the clock cycle that follows the data byte, in order to
indicate that the data has been successfully received. In both cas-
es, the master device must release the SDA line before the ninth
clock cycle, in order to allow this handshaking to occur.
The Read/Write bit is used to determine the data transfer direc-
The Acknowledge bit has two functions. It is used by the mas-
During a data write from the master, the A8290 also pulls SDA
Figure 3. I
SDA
SCL
Start
2
C™ Interface. Read and write sequences.
0
1
0
2
SDA
SCL
SDA
SCL
0
3
Start
Start
Address
Single LNB Supply and Control Voltage Regulator
1
4
0
1
0
1
0
5
A1
0
2
0
2
6
Read Multiple Bytes from Register
A0
0
3
0
3
7
Address
Address
Read One Byte from Register
R
1
4
1
4
1
8
AK
0
5
0
5
9
acknowledge
from LNBR
A1
A1
D7
6
6
Write to Register
A0
D6
A0
7
7
Status Data in Register 1
D5
W
0
8
R
1
8
AK
AK
D4
9
9
acknowledge
from LNBR
acknowledge
from LNBR
same way as in the data write sequence, and then retains control
of the SDA line and send the data from register 1 to the master.
On completion of the eight data bits, the A8290 releases the SDA
line before the ninth clock cycle, in order to allow the master to
acknowledge the data. If the master holds the SDA line low dur-
ing this Acknowledge bit, the A8290 responds by sending the
data from register 2 to the master. Data bytes continue to be sent
to the master until the master releases the SDA line during the
Acknowledge bit. When this is detected, the A8290 stops sending
data and waits for a stop signal.
Interrupt Request
is an open-drain, active-low output. This output may be connect-
ed to a common IRQ line with a suitable external pull-up and can
be used with other I
from the master controller.
D7
D3
I1
During a data read, the A8290 acknowledges the address in the
The A8290 also provides an interrupt request pin, IRQ, which
D6
D2
I0
D5
D5
D1
Status Register 1
Control Data
D4
D4
D0
D3
D3
AK
acknowledge
from LNBR
D2
D2
-
2
C™-compatible devices to request attention
D1
D1
-
Status Data in Register 2
D0
D0
-
115 Northeast Cutoff, Box 15036
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com
NAK
AK
-
acknowledge
from LNBR
no acknowledge
from master
Stop
Stop
D3
D2
D1
D0
NAK
no acknowledge
from master
Stop
10