a8290 Allegro MicroSystems, Inc., a8290 Datasheet - Page 16

• Manufacturer Part Number: a8290
• Description: A8290 Single Lnb Supply And Control Voltage Regulator
• Manufacturer: Allegro MicroSystems, Inc.

A8290
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
DIS
–
OCP
–
PNG
–
TSD
VUV
Single LNB Supply and Control Voltage Regulator
LNB Output Disabled. DIS is used to indicate the current condition of the LNB
output. At power-on, or if a fault condition occurs, DIS will be set. This bit changing
to 1 does not cause the IRQ to activate because the LNB output may be disabled in-
tentionally by the I
if the LNB output is enabled.
Not used.
Overcurrent. If the LNB output detects an overcurrent condition, for greater than
48 ms, the LNB output will be disabled. The OCP bit will be set to indicate that an
overcurrent has occurred and the disable bit, DIS, will be set. The Status register is
updated on the rising edge of the 9
OCP bit is reset in all cases, allowing the master to reenable the LNB output.
Not used.
Power Not Good. Set to 1 when the LNB output is enabled and the LNB voltage is
below 85% of the programmed voltage. The PNG is reset when the LNB volts are
within 90% of the programmed LNB voltage.
Not used.
Thermal shutdown. 1 indicates that the A8290 has detected an overtemperature
condition and has disabled the LNB output. The disable bit, DIS, will also be set.
The status of the overtemperature condition is sampled on the rising edge of the 9
clock pulse in the data read sequence. If the condition is no longer present, then the
TSD bit will be reset, allowing the master to reenable the LNB output if required. If
the condition is still present, then the TSD bit will remain at 1.
Undervoltage Lockout. 1 indicates that the A8290 has detected that the input sup-
ply, V
occurred disabling the LNB outputs. The disable bit, DIS, will also be set and the
A8290 will not reenable the output until so instructed by writing the relevant bit into
the control registers. The status of the undervoltage condition is sampled on the rising
edge of the 9
present, then the VUV bit will be reset allowing the master to reenable the LNB out-
put if required. If the condition is still present, then the VUV bit will remain at 1.
Table 6. Status Register 1
Bit
0
1
2
3
4
5
6
7
IN
is, or has been, below the minimum level and an undervoltage lockout has
Name
OCP
PNG
TSD
VUV
DIS
th
–
–
–
clock pulse in the data read sequence. If the condition is no longer
2
C™ master. This bit will be reset at the end of a write sequence
LNB output disabled
Thermal Shutdown
th
V
Power Not Good
IN
clock pulse in the data read sequence, where the
Overcurrent
Undervoltage
Not Used
Not Used
Not Used
Function
115 Northeast Cutoff, Box 15036
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com
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