lx64eb Lattice Semiconductor Corp., lx64eb Datasheet - Page 8

• Manufacturer Part Number: lx64eb
• Description: High Performance Interfacing And Switching
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 5. ispGDX2-256 sysIO Banks
There are three classes of I/O interface standards implemented in the ispGDX2 devices. The first is the non-termi-
nated, single-ended interface; it includes the 3.3V LVTTL standard along with the 1.8V, 2.5V and 3.3V LVCMOS
interface standards. The slew rate and strength of these output buffers can be controlled individually. Additionally,
PCI 3.3, PCI-X and AGP-1X are all subsets of this interface type. The second interface class implemented is the
terminated, single-ended interface standard. This group of interfaces includes different versions of SSTL and HSTL
interfaces along with CTT and GTL+. Use of these I/O interfaces requires an additional V
level, a termination voltage, V
of the transmission line it is driving. The final types of interfaces implemented are the differential standards
LVPECL, LVDS and Bus LVDS. Table 3 shows the I/O standards supported by the ispGDX2 devices along with
nominal V
The ispGDX2 family also features 5V tolerant I/O. I/O banks with V
mum of 5.5V for easy interfacing with legacy systems. Up to 64 I/O pins per device may be driven by 5V inputs.
CCO
, V
V
V
GND
V
V
GND
CCO5
REF5
CCO6
REF6
REF
and V
TT
.
TT
, is also required. Typically, an output will be terminated to V
sysIO Bank 5
sysIO Bank 6
sysIO Bank 4
sysIO Bank 7
8
sysIO Bank 3
sysIO Bank 0
sysIO Bank 2
sysIO Bank 1
CCO
= 3.3V may have inputs driven to a maxi-
ispGDX2 Family Data Sheet
REF
TT
signal. At the system
V
V
GND
at the receiving end
V
V
GND
CCO1
REF1
CCO2
REF2