lx64eb Lattice Semiconductor Corp., lx64eb Datasheet
lx64eb
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lx64eb Summary of contents
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... I/Os divided by 2. MAX © 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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Lattice Semiconductor Figure 1. ispGDX2 Block Diagram (256-I/O Device) sysHSI Block sysCLOCK PLL sysCLOCK PLL sysHSI Block Introduction The ispGDX2™ family is Lattice’s second generation in-system programmable generic digital crosspoint switch for high speed bus switching and interface applications. The ...
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Lattice Semiconductor The sysIO interfaces provide system-level performance and integration. These I/Os support various modes of LVCMOS/LVTTL and support popular high-speed standard interfaces such as GTL+, PCI-X, HSTL, SSTL, LVDS and Bus-LVDS. The sysHSI Blocks further extend this capability by ...
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Lattice Semiconductor MUX and Register Block (MRB) Every MRB Block has a 4:1 MUX (I/O MUX) and a set of three registers which are connected to the I/O buffers, FIFO and sysHSI Blocks. Multiple MRBs can be combined to form ...
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Lattice Semiconductor Figure 2. GDX Block GRP 32 bits 4 bits 4 bits 4 bits 4 bits 16 bits 16 bits 16 bits The output register of the MRB has a built-in bi-directional shift register capability. Each output register correspond- ...
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Lattice Semiconductor The four data inputs to the 4:1 MUX come from the GRP. The output of this MUX connects to the output register. A fast feedback path from the MUX to the GRP allows wider MUXes to be built. ...
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Lattice Semiconductor Figure 4. ispGDX2 Family Control Array 32 Inputs from Control GRP sysIO Banks The inputs and outputs of ispGDX2 devices are divided into eight sysIO banks, where each bank is capable of sup- porting different I/O standards. The ...
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Lattice Semiconductor Figure 5. ispGDX2-256 sysIO Banks V CCO5 V REF5 GND V CCO6 V REF6 GND There are three classes of I/O interface standards implemented in the ispGDX2 devices. The first is the non-termi- nated, single-ended interface; it includes ...
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Lattice Semiconductor Table 3. ispGDX2 Supported I/O Standards sysIO Standard LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.8 LVTTL PCI 3.3 PCI -X AGP-1X SSTL3 class I & II SSTL2 class I & II CTT 3.3 CTT 2.5 HSTL class I HSTL ...
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Lattice Semiconductor N divider is used to multiply the clock signal. The K divider is used to provide a divided clock frequency of the adja- cent PLL. This output can be routed to the global clock net. The V divider ...
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Lattice Semiconductor Figure 7. I/O Pin Connection to the sysCLOCK PLL Input Clock Programmable GCLK_IN (M) Divider + Delay ÷ -------------------- PLL (n) Programmable - Delay Feedback Divider ( PLL_FBK PLL_RST GCLK_IN 1. ...
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Lattice Semiconductor Figure 8. ispGDX2-64 CLOCK Network sysIO Interface GCLK/CE0 VREF0 CLK_OUT0 GCLK/CE1 VREF1 CLK_OUT2 GCLK/CE2 VREF2 GCLK/CE3 VREF3 Figure 9. ispGDX2-128 CLOCK Network sysIO Interface GCLK/CE0 VREF0 CLK_OUT0 GCLK/CE1 VREF1 CLK_OUT2 GCLK/CE2 VREF2 GCLK/CE3 VREF3 sysCLOCK CLK0 K(0) PLL ...
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Lattice Semiconductor Figure 10. ispGDX2-256 CLOCK Network sysIO Interface GCLK/CE0 + VREF0 - CLK_OUT0 GCLK/CE1 + - VREF1 CLK_OUT1 GCLK/CE2 + VREF2 - CLK_OUT2 GCLK/CE3 + - VREF3 CLK_OUT3 ispGDX2 Family Data Sheet sysCLOCK CLK0 K(0) PLL (0) CLK1 K(1) ...
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Lattice Semiconductor Operating Modes All the GDX Blocks in the ispGDX2 family can be programmed in four modes: Basic, FIFO only, SERDES only, and FIFO with SERDES mode. In basic mode, the SERDES and FIFO are disabled and the MUX ...
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Lattice Semiconductor Figure 12. ispGDX2 FIFO Signals Data Out (DOUT) Read Clock (RCLK) Read Enable (RE) Global Reset (RESETb) Power-on Reset (PORb) FIFO Reset (FIFORSTb) Read Clock and Read Enable are the same as the Clock and Clock Enable signals ...
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Lattice Semiconductor Figure 13. Operation in FIFO Mode GRP GDX Block Input Reg/ Latch Output Reg/ Latch Input Reg/ Latch Input Reg/ Latch Output Reg/ Latch Output Reg/ Latch Notes: 1. For clarity, only a portion of the GDX Block ...
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Lattice Semiconductor High Speed Serial Interface Block (sysHSI Block) The High Speed Serial Interface (sysHSI) allows high speed serial data transfer over a pair of LVDS I/O. The ispGDX2 devices have multiple sysHSI Blocks. Each sysHSI Block has two SERDES ...
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Lattice Semiconductor Figure 14. sysHSI Block with SERDES and FIFO SOUT SIN CSLOCK SS_CLKOUT SS_CLKIN CAL Shared Source Synchronous pins drive multiple sysHSI blocks SOUT SIN Note: Some pins are shared. See Logic Signal Connections table for details sysHSI Block ...
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Lattice Semiconductor Figure 15. Operation in SERDES Only Mode GRP GDX Block Input Reg/ Latch Output Reg/ Latch Input Reg/ Latch Input Reg/ Latch Output Reg/ Latch Output Reg/ Latch Notes: 1. Some pins shared. See Logic Signal Connections table ...
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Lattice Semiconductor Figure 16. Operation in SERDES with FIFO Mode GRP GDX Block Input Reg/ Latch Output Reg/ Latch Input Reg/ Latch Input Reg/ Latch Output Reg/ Latch Output Reg/ Latch FIFO 10 Delay DIN DOUT RCLK RE 10 PT-CLK/CE(0:3) ...
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Lattice Semiconductor IEEE 1149.1-Compliant Boundary Scan Testability All ispGDX2 devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows func- tional testing of the circuit board on which the device is mounted through a serial ...
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Lattice Semiconductor Absolute Maximum Ratings Supply Voltage -0 ...
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Lattice Semiconductor DC Electrical Characteristics Symbol Parameter Input or I/O Low Leakage Input High Leakage Current IH I I/O Active Pull-up Current PU I I/O Active Pull-down Current PD I Bus Hold ...
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Lattice Semiconductor sysIO Recommended Operating Conditions Standard Min. LVCMOS 3.3 3.0 LVCMOS 2.5 2.3 2 LVCMOS 1.8 1.65 LVTTL 3.0 PCI 3.3 3.0 PCI-X 3.0 AGP-1X 3.15 SSTL 2 2.3 SSTL 3 3.0 CTT 3.3 3.0 CTT 2.5 2.3 HSTL ...
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Lattice Semiconductor sysIO Single Ended DC Electrical Characteristics V IL Input/Output Standard Min (V) Max (V) LVCMOS 3.3 -0.3 0.8 LVTTL -0.3 0.8 LVCMOS 2.5 -0.3 0 LVCMOS 1.8 -0.3 0.68 3 LVCMOS 1.8 -0.3 0.68 4 PCI ...
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Lattice Semiconductor sysIO Differential DC Electrical Characteristics Parameter Symbol Parameter Description LVDS V V Input Voltage INP INM V Differential Input Threshold THD I Input Current IN V Output High Voltage for Output Low Voltage for V ...
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Lattice Semiconductor ispGDX2V/B/C, ispGDX2EV/EB/EC External Switching Characteristics Parameter Description Output Paths t Data From Input Pin to Output Pin PD t Data From Global Select Pin to Output Pin PD_SEL t Global Clock to Output CO t Set-up Time Before ...
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Lattice Semiconductor ispGDX2V/B/C, ispGDX2EV/EB/EC External Switching Characteristics Parameter Description f Clock Frequency Maximum Toggle MAX (Tog, PLL) (With PLL) Over Recommended Operating Conditions -3 Min. Max. Min. — 360 28 ispGDX2 Family Data Sheet -32 -35 -5 Max. Min. Max. ...
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Lattice Semiconductor Timing Model The task of determining the timing through the ispGDX2 family is relatively simple. The timing model provided in Figure 18 shows the specific delay paths. Once the implementation of a given function is determined either con- ...
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Lattice Semiconductor Figure 19. ispGDX2 Timing Model Diagram (with sysHSI and FIFO Receive Mode) Serial Data from I/O Cell t In (SIN) HSISIN HSI Controls from I/O Cell t CAL HSICTRLCAL (Control) from I/O Cell Source t (SSCLKIN) HSISSCLKIN Synchronous ...
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Lattice Semiconductor Figure 21. ispGDX2 Timing Model Diagram (in FIFO Only Mode) from I/O Cell (DIN) from I/O Cell (WCLK) from I/O Cell (WE) from I/O Cell (RCLK) from I/O Cell (RE) from I/O Cell (Global RESET) from I/O Cell ...
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Lattice Semiconductor Sample External Timing Calculations The following equations illustrate the task of determining the timing through the ispGDX2 family. These are only a sample of equations to calculate the timing through the ispGDX2. Figure 18 shows the specific delay ...
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Lattice Semiconductor ispGDX2V/B/C, ispGDX2EV/EB/EC Internal Timing Parameters Parameter Description Input/Output Delays t Output Buffer Delay BUF t Global Clock Input Delay CLK_IN t Global Clock Enable Input Delay CLKEN_IN t Output Disable Delay DIS t Output Enable Delay EN t ...
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Lattice Semiconductor ispGDX2V/B/C, ispGDX2EV/EB/EC Internal Timing Parameters Parameter Description t Latch Gate to Output Delay OPLGOi t Latch Hold Time OPLHi Latch Propagation Delay (Transparent t OPLPDi Mode) t Latch Setup Time (Global Gate) OPLSi t Latch Setup Time (Product ...
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Lattice Semiconductor ispGDX2V/B/C, ispGDX2EV/EB/EC Internal Timing Parameters Parameter Description t Latch Setup Time (Global Gate) OELSi t Latch Setup Time (Product Term Gate) OELSi_PT t Register Setup Time (Global Clock) OESi t Register Setup Time (Product Term Clock) OESi_PT t ...
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Lattice Semiconductor ispGDX2V/B/C, ispGDX2EV/EB/EC Timing Adjusters Parameter Optional Adders t Input Delay INDIO Secondary PLL Output t PLL_SEC_DELAY Delay t Output Adjusters IOO Using Slow Slew (LVTTL and Slow Slew LVCMOS Outputs Only) LVTTL_out Using 3.3V TTL Drive Using 1.8V ...
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Lattice Semiconductor ispGDX2V/B/C, ispGDX2EV/EB/EC Timing Adjusters (Continued) Parameter Using LVPECL Differential LVPECL_out Signaling Using Low Voltage Differen- LVDS_out tial Signaling (LVDS) PCI_out Using PCI Standard PCI_X_out Using PCI-X Standard SSTL2_I_out Using SSTL 2.5V, Class I SSTL2_II_out Using SSTL 2.5V, Class ...
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Lattice Semiconductor ispGDX2V/B/C, ispGDX2EV/EB/EC FIFO Internal Timing Parameter Description Routing Delays t FIFO Input Delay FIFODATAIN t FIFO Output to I/O Core Delay FIFODATAOUT t Read Clock Input Delay FIFORCLK t Read Clock Enable Input Delay FIFOREN t Write Clock ...
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Lattice Semiconductor sysHSI Block Timing Figure 22 provides a graphical representation of the SERDES receiver input requirements. It provides guidance on a number of input parameters, including signal amplitude and rise time limits, noise and jitter limits, and P and ...
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Lattice Semiconductor LOCKIN Time Symbol Description t CSPLL Lock Time SCLOCK t CDRPLL Lock-in Time CDRLOCK t SyncPat Length SYNC t CAL Duration CAL t SyncPat Set-up Time to CAL SUSYNC t SyncPat Hold Time from CAL HDSYNC 1. REFCLK ...
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Lattice Semiconductor Deserializer Timing Symbol Description f SIN Frequency Deviation from REFCLK DSIN eo SIN Eye Opening Tolerance SIN ber Bit Error Rate RXD, SYDT Valid Time Before RECCLK Fall- t HSIOUTVALIDPRE ing Edge RXD, SYDT Valid Time t HSIOUTVALIDPOST ...
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Lattice Semiconductor Lock-in Timing (Continued) CDR_8B10B LOCK-IN TIMING SI N SYDT RXD(0:9) SYDT Timing SYDT TIMING FOR CDRX_10B12B RECCLK SYDT RXD(0:9) SYDT TIMING FOR CDRX_8B10B RECCLK SYDT RXD(0:9) 240 Idle Pattern(960 TRCP) DATA (SERIAL ) Idle Pattern DATA (PARALLEL) Data0 ...
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Lattice Semiconductor Serializer Timing 8B/10B SERIALIZER DELAY TIMING TXD REFCLK SOUT SYMBOL N-1 10B/12B SERIALIZER DELAY TIMING TXD REFCLK SOUT SS Mode SERIALIZER DELAY TIMING TXD REFCLK SS_CLKOUT b4 SOUT ...
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Lattice Semiconductor Deserializer Timing 8B/10B DESERIALIZER DELAY TIMING SYMBOL SIN RECCLK RXD 10B/12B DESERIALIZER DELAY TIMING SIN "1" RECCLK RXD SYMBOL N-2 CDRX_SS DESERIALIZER DELAY TIMING SYMBOL SIN ...
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Lattice Semiconductor sysCLOCK PLL Timing Symbol Parameter t Input clock, high time PWH t Input clock, low time PWL Input Clock, rise and fall time Input clock stability, cycle to cycle (peak) INSTB f ...
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Lattice Semiconductor Boundary Scan Timing Specifications Parameter t TCK [BSCAN] clock pulse width BTCP t TCK [BSCAN] clock pulse width high BTCPH t TCK [BSCAN] clock pulse width low BTCPL t TCK [BSCAN] setup time BTS t TCK [BSCAN] hold ...
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Lattice Semiconductor Power Consumption I CORE 200 150 100 100 150 200 250 300 MHz Power Estimation Coefficients – Core and PLL Device 3.3 ispGDX2-256 2.5 1 Blank chip background current ...
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Lattice Semiconductor Power Consumption (Continued) Power consumption in the ispGDX2 family is the sum of three components CC-TOTAL CORE PLL CORE DC REF IN = Blank chip background ...
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Lattice Semiconductor Switching Test Conditions Figure 23 shows the output test load used for AC testing. Specific values for resistance, capacitance, voltage and other test conditions are shown in Table 7. Figure 23. Output Test Load, LVTTL and LVCMOS Standards ...
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Lattice Semiconductor 1 Signal Descriptions Signal Names General Purpose BKx_IOy GCLK/CE0, GCLK/CE1, GCLK/CE2, GCLK/CE3 2 2 SEL0, SEL1, SEL2 , SEL3 2 2 GOE0, GOE1, GOE2 , GOE3 RESETb NC GND CCJ V x CCO V x ...
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Lattice Semiconductor 1 Signal Descriptions (Continued) Signal Names w HSImA_TXDw, HSImB_ TXD w HSImA_RXDw, HSImB_ RXD Source Synchronous Functions SS_SCLKIN0P, SS_SCLKIN1P SS_SCLKIN0N, SS_SCLKIN1N SS_CLKOUT0N, SS_CLKOUT1P SS_CLKOUT0N, SS_CLKOUT1N CAL and z are variables. 2. Not on ...
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Lattice Semiconductor ispGDX2 Power Supply and NC Connections Signal ispGDX2-128 (208-Ball fpBGA) V B15, C14, R15, B2, C3, P3, R2 N11, T12 CCO0 V L13, M16 CCO1 V E16, F13 CCO2 V A12, D11 CCO3 V A5, D6 ...
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Lattice Semiconductor ispGDX2-64 Logic Signal Connections sysIO LVDS Signal Name Bank Pair/Polarity GOE0 - - BK0_IO0/PLL_LOCK0 0 0N BK0_IO1 0 0P GND 0 - BK0_IO2 0 1N BK0_IO3 0 1P GND 0 - BK0_IO4/PLL_RST0 0 2N BK0_IO5 0 2P BK0_IO6 ...
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Lattice Semiconductor ispGDX2-64 Logic Signal Connections (Continued) sysIO LVDS Signal Name Bank Pair/Polarity SEL0 - - SEL1 - - BK4_IO0/CLK_OUT2 4 16N BK4_IO1 4 16P GND 4 - BK4_IO2 4 17N BK4_IO3 4 17P GND 4 BK4_IO4 4 18N BK4_IO5 ...
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Lattice Semiconductor ispGDX2-64 Logic Signal Connections (Continued) sysIO LVDS Signal Name Bank Pair/Polarity GND 7 - BK7_IO6 7 31P BK7_IO7/PLL_LOCK2 7 31N GOE1 The signals in this column route to/from the assigned pins of the associated I/O ...
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Lattice Semiconductor ispGDX2-128 Logic Signal Connections sysIO LVDS Signal Name Bank Pair/Polarity TOE - BK0_IO0 0 0N BK0_IO1 0 0P BK0_IO2 / PLL_LOCK2 / 0 1N PLL_RST2 BK0_IO3 0 1P GND 0 BK0_IO4 0 2N BK0_IO5 0 2P BK0_IO6 0 ...
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Lattice Semiconductor ispGDX2-128 Logic Signal Connections (Continued) sysIO LVDS Signal Name Bank Pair/Polarity BK2_IO3 2 17P GND 2 BK2_IO4 2 18N BK2_IO5 2 18P BK2_IO6 2 19N BK2_IO7 2 19P BK2_IO8 2 20N BK2_IO9 2 20P BK2_IO10 2 21N BK2_IO11 ...
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Lattice Semiconductor ispGDX2-128 Logic Signal Connections (Continued) sysIO LVDS Signal Name Bank Pair/Polarity BK4_IO8 4 36N BK4_IO9 / PLL_FB0 4 36P BK4_IO10 4 37N BK4_IO11 4 37P GND 4 BK4_IO12 4 38N BK4_IO13 4 38P BK4_IO14 4 39N BK4_IO15 / ...
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Lattice Semiconductor ispGDX2-128 Logic Signal Connections (Continued) sysIO LVDS Signal Name Bank Pair/Polarity GND 6 BK6_IO12 6 54N BK6_IO13 6 54P BK6_IO14 6 55N BK6_IO15 / VREF6 6 55P TDI - GOE0 - GND 7 BK7_IO0 / VREF7 7 56P ...
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Lattice Semiconductor ispGDX2-256 Logic Signal Connections Signal sysIO LVDS Name Bank Pair/Polarity Block MRB BK0_IO0 0 0N BK0_IO1 0 0P BK0_IO2 PLL_LOCK2 BK0_IO3 0 1P GND 0 - BK0_IO4 0 2N BK0_IO5 0 2P BK0_IO6 0 3N BK0_IO7 ...
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Lattice Semiconductor ispGDX2-256 Logic Signal Connections (Continued) Signal sysIO LVDS Name Bank Pair/Polarity Block MRB BK1_IO5 1 18N BK1_IO6 1 19P BK1_IO7 1 19N BK1_IO8 1 20P BK1_IO9 1 20N BK1_IO10/ 1 21P VREF1 BK1_IO11 1 21N GND 1 - ...
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Lattice Semiconductor ispGDX2-256 Logic Signal Connections (Continued) Signal sysIO LVDS Name Bank Pair/Polarity Block MRB BK2_IO10 2 37N BK2_IO11 2 37P GND 2 - BK2_IO12 2 38N BK2_IO13 2 38P BK2_IO14 2 39N BK2_IO15 2 39P BK2_IO16 2 40N BK2_IO17 ...
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Lattice Semiconductor ispGDX2-256 Logic Signal Connections (Continued) Signal sysIO LVDS Name Bank Pair/Polarity Block MRB BK3_IO15 3 55N BK3_IO16 3 56P BK3_IO17 3 56N BK3_IO18 3 57P BK3_IO19 3 57N GND 3 - BK3_IO20 3 58P BK3_IO21 3 58N BK3_IO22 ...
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Lattice Semiconductor ispGDX2-256 Logic Signal Connections (Continued) Signal sysIO LVDS Name Bank Pair/Polarity Block MRB BK4_IO21/ 4 74P VREF4 BK4_IO22 4 75N BK4_IO23 4 75P BK4_IO24 4 76N BK4_IO25 4 76P BK4_IO26 4 77N BK4_IO27 4 77P BK4_IO28 4 78N ...
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Lattice Semiconductor ispGDX2-256 Logic Signal Connections (Continued) Signal sysIO LVDS Name Bank Pair/Polarity Block MRB GND 5 - BK5_IO28 5 94P BK5_IO29 5 94N BK5_IO30 5 95P BK5_IO31/ 5 95N CLK_OUT0 GCLK/CE0 - CLK0P SEL0 - - SEL1 - - ...
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Lattice Semiconductor ispGDX2-256 Logic Signal Connections (Continued) Signal sysIO LVDS Name Bank Pair/Polarity Block MRB GND 6 - TDI - - GOE0 - - GND 7 - BK7_IO0 7 112P BK7_IO1 7 112N BK7_IO2 7 113P BK7_IO3 7 113N BK7_IO4 ...
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Lattice Semiconductor ispGDX2-256 Logic Signal Connections (Continued) Signal sysIO LVDS Name Bank Pair/Polarity Block MRB TOE - - 1. The signals in this column route to/from the assigned pins of the associated I/O cell. 2. The signals in this column ...
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Lattice Semiconductor Part Number Description LX XXX X X – XX FXXX X Device Family LX Device Number I/Os 128 = 128 I/Os 256 = 256 I/Os sysHSI Support Blank = Supports sysHSI sysHSI ...
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... LX64EB-5F100C LX128EB-32F208C LX128EB LX128EB-5F208C LX256EB-35F484C LX256EB LX256EB-5F484C LX64EC-3F100C LX64EC LX64EC-5F100C LX128EC-32F208C LX128EC LX128EC-5F208C Family Part Number LX64EV LX64EV-5F100I LX64EB LX64EB-5F100I LX64EC LX64EC-5F100I LX128EV LX128EV-5F208I LX128EB LX128EB-5F208I LX128EC LX128EC-5F208I LX256EV LX256EV-5F484I LX256EB LX256EB-5F484I LX256EC LX256EC-5F484I “E-Series” Commercial I/Os Voltage 3 ...
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... LX128B-5FN208C LX128C-32FN208C LX128C LX128C-5FN208C LX256V-35FN484C LX256V LX256V-5FN484C LX256B-35FN484C LX256B LX256B-5FN484C LX256C-35FN484C LX256C LX256C-5FN484C Family Part Number LX64EV-3FN100C LX64EV LX64EV-5FN100C LX64EB-3FN100C LX64EB LX64EB-5FN100C LX64EC-3FN100C LX64EC LX64EC-5FN100C LX128EV-32FN208C LX128EV LX128EV-5FN208C LX128EB-32FN208C LX128EB LX128EB-5FN208C LX128EC-32FN208C LX128EC LX128EC-5FN208C LX256EV-35FN484C LX256EV LX256EV-5FN484C LX256EB-35FN484C LX256EB LX256EB-5FN484C LX256EC-35FN484C ...
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... Lattice Semiconductor Family Part Number LX64EV LX64EV-5FN100I LX64EB LX64EB-5FN100I LX64EC LX64EC-5FN100I LX128EV LX128EV-5FN208I LX128EB LX128EB-5FN208I LX128EC LX128EC-5FN208I LX256EV LX256EV-5FN484I LX256EB LX256EB-5FN484I LX256EC LX256EC-5FN484I “E-Series” Industrial I/Os Voltage 3.3 5.0 64 2.5 5.0 64 1.8 5.0 128 3.3 5.0 128 2.5 5.0 128 1.8 5.0 256 3.3 5.0 256 2.5 5.0 256 1.8 5.0 71 ispGDX2 Family Data Sheet Package ...
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Lattice Semiconductor For Further Information In addition to this data sheet, the following Lattice technical notes may be helpful when designing with the ispGDX2 Family: • sysIO Design and Usage Guidelines (TN1000) • sysCLOCK PLL Design and Usage Guidelines (TN1003) ...