lx64eb Lattice Semiconductor Corp., lx64eb Datasheet - Page 11

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lx64eb

Manufacturer Part Number
lx64eb
Description
High Performance Interfacing And Switching
Manufacturer
Lattice Semiconductor Corp.
Datasheet
Lattice Semiconductor
Figure 7. I/O Pin Connection to the sysCLOCK PLL
GCLK_IN
1. Some pins are shared. See Logic Signal Connections Table for details.
GCLK_IN
Input Clock
(M) Divider
÷ 1 to 32
PLL_RST
--------------------
Programmable
Programmable
Divider (N)
Feedback
x 1 to 32
+ Delay
- Delay
PLL_FBK
PLL (n)
Post-scalar
(V) Divider
(K) Divider
1, 2, 4, 8,
2, 4, 8,
16, 32
16, 32
Clock
÷
÷
To Adjacent_PLL
From Adjacent_PLL
Clock Net
PLL_LOCK
1
CLK_OUT
11
GRP
Resetb (0)
(from selected blocks)
Control Array
ispGDX2 Family Data Sheet
GDX Block
Output
Latch
Input
Reg/
Latch
Reg/
Delay

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