W83977A Winbond Electronics Corp America, W83977A Datasheet - Page 51

• Manufacturer Part Number: W83977A
• Description: Winbond I/O
• Manufacturer: Winbond Electronics Corp America

Bit 6: TSRE. In 16450 mode, when TBR and TSR are both empty, this bit will be set to a logical 1. In
Bit 5: TBRE. In 16450 mode, when a data character is transferred from TBR to TSR, this bit will be set to
Bit 4: SBD. This bit is set to a logical 1 to indicate that received data are kept in silent state for a full word
Bit 3: NSER. This bit is set to a logical 1 to indicate that the received data have no stop bit. In 16550
Bit 2: PBER. This bit is set to a logical 1 to indicate that the parity bit of received data is wrong. In 16550
Bit 1: OER. This bit is set to a logical 1 to indicate received data have been overwritten by the next
Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in the
3.2.3 Handshake Control Register (HCR) (Read/Write)
This register controls the pins of the UART used for handshaking peripherals such as modem, and
controls the diagnostic mode of the UART.
16550 mode, if the transmit FIFO and TSR are both empty, it will be set to a logical 1. Other
thanthese two cases, this bit will be reset to a logical 0.
a logical 1. If ETREI of ICR is a logical 1, an interrupt will be generated to notify the CPU to write
the next data. In 16550 mode, this bit will be set to a logical 1 when the transmit FIFO is empty. It
will be reset to a logical 0 when the CPU writes data into TBR or FIFO.
time, including start bit, data bits, parity bit, and stop bits. In 16550 mode, it indicates the same
condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a
logical 0.
mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR,
it will clear this bit to a logical 0.
mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR,
it will clear this bit to a logical 0.
received data before they were read by the CPU. In 16550 mode, it indicates the same condition
instead of FIFO full. When the CPU reads USR, it will clear this bit to a logical 0.
RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0.
7
0
0
6
5
0
4
3
2
1
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0
Data terminal ready (DTR)
Request to send (RTS)
Loopback RI input
IRQ enable
Internal loopback enable
Publication Release Date: March 1998
W83977TF
PRELIMINARY
Revision 0.62