W83977A Winbond Electronics Corp America, W83977A Datasheet - Page 49

• Manufacturer Part Number: W83977A
• Description: Winbond I/O
• Manufacturer: Winbond Electronics Corp America

BDLAB = 0
BDLAB = 0
BDLAB = 0
BDLAB = 1
BDLAB = 1
Register Address Base
+ 0
+ 0
+ 1
+ 2
+ 2
+ 3
+ 4
+ 5
+ 6
+ 7
+ 0
+ 1
TABLE 3-1 UART Register Bit Map
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.
Interrupt Status
Buffer Register
Status Register
UART Control
Divisor Latch
Divisor Latch
User Defined
UART Status
(Write Only)
(Write Only)
(Read Only)
Transmitter
(Read Only)
UART FIFO
Handshake
Handshake
Baudrate
Receiver
Interrupt
Register
Register
Register
Register
Register
Register
Register
Register
Baudrate
Control
Control
Control
Buffer
High
Low
RBR
UCR
HCR
UDR
TBR
UFR
USR
HSR
BLL
BHL
ICR
ISR
"0" if Interrupt
RBR Data
RBR Data
RX Data
TX Data
(ERDRI)
Terminal
Toggling
Interrupt
Pending
(TCTS)
(DLS0)
Enable
Enable
Length
(RDR)
Ready
Select
Ready
(DTR)
Ready
FIFO
Bit 0
Bit 0
Data
Bit 0
Data
CTS
Bit 0
Bit 0
Bit 8
0
(ETBREI)
RX Data
TX Data
Interrupt
Interrupt
Request
Toggling
Overrun
(TDSR)
(DLS1)
Enable
RCVR
Length
(OER)
Empty
Status
Bit (0)
Select
(RTS)
Reset
FIFO
Send
Error
DSR
Bit 1
Bit 1
TBR
Data
Bit 1
Bit 1
Bit 1
Bit 9
to
1
Loopback
RI Falling
Stop Bits
Parity Bit
RX Data
TX Data
(EUSRI)
Interrupt
(MSBE)
(PBER)
Interrupt
Multiple
Enable
Enable
(FERI)
Status
Bit (1)
XMIT
Reset
Bit 10
FIFO
Input
Error
Edge
Bit 2
Bit 2
Bit 2
Bit 2
USR
RI
2
- 41 -
Bit Number
RX Data
(EHSRI)
TX Data
Interrupt
Interrupt
Toggling
No Stop
(NSER)
(TDCD)
Bit (2)**
Enable
Enable
Enable
Status
Select
(PBE)
Parity
Bit 11
DMA
Mode
Error
DCD
HSR
Bit 3
Bit 3
Bit 3
Bit 3
IRQ
Bit
Bit
3
Publication Release Date: March 1998
Reserved
Loopback
Detected
RX Data
TX Data
Internal
to Send
Enable
Enable
(EPE)
(SBD)
(CTS)
Bit 12
Parity
Silent
Clear
Even
Bit 4
Bit 4
Bit 4
Bit 4
Byte
4
0
0
W83977TF
PRELIMINARY
Reversed
RX Data
TX Data
Bit Fixed
Data Set
(TBRE)
Enable
PBFE)
(DSR)
Empty
Ready
Parity
Bit 13
TBR
Bit 5
Bit 5
Bit 5
Bit 5
5
0
0
0
Revision 0.62
Active Level
RX Data
TX Data
Interrupt
Indicator
Enabled
(TSRE)
Silence
Enable
FIFOs
(SSE)
Empty
(LSB)
Bit 14
Bit 6
Bit 6
TSR
Ring
Bit 6
Bit 6
(RI)
Set
RX
**
6
0
0
Data Carrier
Active Level
Access Bit
Indication
RX Data
Baudrate
(BDLAB)
RX FIFO
(RFEI) **
TX Data
Interrupt
Enabled
(MSB)
Divisor
(DCD)
FIFOs
Detect
Latch
Bit 15
Error
Bit 7
Bit 7
Bit 7
Bit 7
RX
**
7
0
0