W83877 Winbond Electronics Corp America, W83877 Datasheet - Page 5

• Manufacturer Part Number: W83877
• Description: Winbond I/O
• Manufacturer: Winbond Electronics Corp America

1.0 PIN DESCRIPTION
Note: Refer to section 9.2 DC CHARACTERISTICS for details.
I/O8t - TTL level bidirectional pin with 8 mA source-sink capability
I/O12t - TTL level bidirectional pin with 12 mA source-sink capability
I/O24t - TTL level bidirectional pin with 24 mA source-sink capability
OUT8t - TTL level output pin with 8 mA source-sink capability
OUT12t - TTL level output pin with 12 mA source-sink capability
OD12 - Open-drain output pin with 12 mA sink capability
OD24 - Open-drain output pin with 24 mA sink capability
INt
INc
INcs - CMOS level schmitt-triggered input pin
1.1 Host Interface
D0 D7
A0 A9
A10
IOCHRDY
MR
AEN
DRQ_B
DRQ_C
TC
CS
IOR
IOW
DACK_B
DACK_ C
IRQIN
SYMBOL
- TTL level input pin
- CMOS level input pin
66-73
51-55
57-61
PIN
100
75
62
63
64
98
18
97
93
5
6
2
4
OUT
OUT
I/O
OD
IN
IN
IN
I/O
IN
IN
IN
IN
IN
IN
IN
IN
cs
cs
cs
24t
c
c
c
c
c
c
c
24
t
12t
12t
System data bus bits 0-7
System address bus bits 0-9
In ECP Mode, this pin is the A10 address input.
In EPP Mode, this pin is the IO Channel Ready output to extend
the host read/write cycle.
Master Reset. Active high. MR is low during normal operations.
Active low chip select signal
System address bus enable
CPU I/O read signal
CPU I/O write signal
DMA request signal B
DMA Acknowledge signal B
DMA request signal C
DMA Acknowledge signal C
Terminal Count. When active, this pin indicates termination of a
DMA transfer.
Interrupt request input
- 5 -
FUNCTION
Publication Release Date: January 1996
W83877F
Revision A2