W83627F Information Storage Devices, Inc, W83627F Datasheet - Page 96

• Manufacturer Part Number: W83627F
• Description: LPC Interface I/o Plus Kbc, Game Port, Midi Port
• Manufacturer: Information Storage Devices, Inc

CRE1 (Default 0x00) Keyboard Wake-Up Index Register
This register is used to indicate which Keyboard Wake-Up Shift register or Predetermined key Register
is to be read/written via CRE2. The range of Keyboard wake-up index register is 0x00 - 0x19, and the
range of CIR wake-up index register is 0x20 - 0x2F.
CRE2 Keyboard Wake-Up Data Register
This register holds the value of wake-up key register indicated by CRE1. This register can be
CRE3 (Read only) Keyboard/Mouse Wake-Up Status Register
CRE4 (Default 0x00)
read/written.
Bit 7-6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6-5
Bit 4
Bit 3
Bit 2
Bit 1 - 0 : Reserved.
: Reserved.
: When 1 is VSB Power Loss status.
:PWRLOSS_STS: This bit is set when power loss occurs. This bit is control by CR E4, bit
:CIR_STS. The Panel switch event is caused by CIR wake-up event. This bit is cleared by
reading this register.
:PANSW_STS. The Panel switch event is caused by PANSW_IN. This bit is cleared by
reading this register.
:Mouse_STS. The Panel switch event is caused by Mouse wake-up event. This bit is
cleared by reading this register.
:Keyboard_STS. The Panel switch event is caused by Keyboard wake-up event. This bit is
cleared by reading this register.
: Power loss control bit 2.
0 = Disable ACPI resume
1 = Enable ACPI resume
: Power loss control bit <1:0>
00 = System always turn off when come back from power loss state.
01 = System always turn on when come back from power loss state.
10 = System turn on/off when come back from power loss state depend on the state
before power loss.
11 = Reserved.
: Suspend clock source select
0 = Use internal clock source.
1 = Use external suspend clock source(32.768KHz).
: Keyboard wake-up type select for wake-up the system from S1/S2.
0 = Password or Hot keys programmed in the registers.
1 =Any key.
: Enable all wake-up event set in CRE0 can wake-up the system from S1/S2 state. This
bit is cleared when wake-up event occurs.
0 = Disable.
1 = Enable.
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Publication Release Date:November 2002
W83627HF/F
Revision 2.0