W83627F Information Storage Devices, Inc, W83627F Datasheet - Page 79

• Manufacturer Part Number: W83627F
• Description: LPC Interface I/o Plus Kbc, Game Port, Midi Port
• Manufacturer: Information Storage Devices, Inc

CR23 (Default 0x00)
CR24 (Default 0b1s000s0s)
CR25 (Default 0x00)
Bit 7 - 1
Bit 0
Bit 7
Bit 6
Bit 5 - 3 : Reserved
Bit 2
Bit 1
Bit 0
When trying to make a change to this bit, new value of PNPCVS must be complementary to the old
one to make an effective change. For example, the user must set PNPCVS to 0 first and then reset
it to 1 to reset these PnP registers if the present value of PNPCVS is 1. The
power-on setting pin is NDTRA (pin 52).
Bit 7 - 6 : Reserved
Bit 5
Bit 4
Bit 3
Bit 2 - 1 : Reserved
Bit 0
: IPD (Immediate Power Down). When set to 1, it will put the whole chip into power down
mode immediately.
: EN16SA
= 0 12 bit Address Qualification
= 1 16 bit Address Qualification
:CLKSEL
= 0 The clock input on Pin 1 should be 24 Mhz.
= 1 The clock input on Pin 1 should be 48 Mhz.
The corresponding power-on setting pin is SOUTB (pin 83).
: ENKBC
= 0 KBC is disabled after hardware reset.
= 1 KBC is enabled after hardware reset.
This bit is read only, and set/reset by power-on setting pin. The corresponding power-on
setting pin is SOUTA (pin 54).
: Reserved
: PNPCVS
= 0 The Compatible PnP address select registers have default values.
= 1 The Compatible PnP address select registers have no default value.
: URBTRI
: URATRI
: PRTTRI
: FDCTRI.
: Reserved.
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Publication Release Date:November 2002
W83627HF/F
corresponding
Revision 2.0