W83627F Information Storage Devices, Inc, W83627F Datasheet - Page 88

• Manufacturer Part Number: W83627F
• Description: LPC Interface I/o Plus Kbc, Game Port, Midi Port
• Manufacturer: Information Storage Devices, Inc

4.4 Logical Device 2 (UART A)
CR30 (Default 0x01 if PNPCVS = 0 during POR, default 0x00 otherwise)
CR60, CR 61 (Default 0x03, 0xF8 if PNPCVS = 0 during POR, default 0x00, 0x00 otherwise)
CR70 (Default 0x04 if PNPCVS = 0 during POR, default 0x00 otherwise)
CRF0 (Default 0x00)
4.5 Logical Device 3 (UART B)
CR30 (Default 0x01 if PNPCVS = 0 during POR, default 0x00 otherwise)
CR60, CR 61 (Default 0x02, 0xF8 if PNPCVS = 0 during POR, default 0x00, 0x00 otherwise)
CR70 (Default 0x03 if PNPCVS = 0 during POR, default 0x00 otherwise)
These two registers select Serial Port 1 I/O base address [0x100:0xFF8] on 8 byte boundary.
These two registers select Serial Port 2 I/O base address [0x100:0xFF8] on 8 byte boundary.
Bit 7 - 1 : Reserved.
Bit 0
Bit 7 - 4 : Reserved.
Bit 3 - 0 : These bits select IRQ resource for Serial Port 1.
Bit 7 - 2 : Reserved.
Bit 1 - 0 : SUACLKB1, SUACLKB0
Bit 7 - 1 : Reserved.
Bit 0
Bit 7 - 4 : Reserved.
Bit [3:0] : These bits select IRQ resource for Serial Port 2.
= 1 Activates the logical device.
= 0 Logical device is inactive.
= 00
= 01
= 10
= 11
= 1 Activates the logical device.
= 0 Logical device is inactive.
UART A clock source is 1.8462 Mhz (24MHz/13)
UART A clock source is 2 Mhz (24MHz/12)
UART A clock source is 24 Mhz (24MHz/1)
UART A clock source is 14.769 Mhz (24mhz/1.625)
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Publication Release Date:November 2002
W83627HF/F
Revision 2.0