W134 Cypress Semiconductor Corp., W134 Datasheet - Page 6

• Manufacturer Part Number: W134
• Description: 400 MHZ DRCG
• Manufacturer: Cypress Semiconductor Corp.

Timing Diagrams
The control signals Mult0 and Mult1 can be used in two ways.
If they are changed during Power-down mode, then the Power-
down transition timings determine the settling time of the
DRCG. However, the Mult0 and Mult1 control signals can also
be changed during Normal mode. When the Mult control sig-
nals are “hot swapped” in this manner, the Mult transition tim-
ings determine the settling time of the DRCG.
In Clock Stop mode, the clock source is on, but the output is
disabled (StopB asserted). The V
remain on or may be grounded during the Clk Stop mode. The
V
mode.
In Normal mode, the clock source is on, and the output is en-
abled.
Table 7 lists the control signals for each state.
Document #: 38-07426 Rev. **
Mult0 and/or Mult1
Clk/ClkB
DDR
reference input must remain on during the Clock Stop
Output Enable Control
PwrDnB
Clk/ClkB
Clk/ClkB
Power-Down Exit and Entry
StopB
Output clock
not specified
glitches may
occur
DDPD
t
CLKON
t
Figure 5. State Transition Timing Diagrams
POWERUP
reference input may
Clock enabled
and glitch free
t
CLKSETL
Figure 6. Multiply Transition Timing
t
ON
t
MULT
Clock output settled within
50 ps of the phase before
disabled
Table 7. Control Signals for Clock Source States
Figure 5 shows the timing diagrams for the various transitions
between states, and Table 8 specifies the latencies of each
state transition. Note that these transition latencies assume
the following:
• Refclk input has settled and meets specification shown in
• Mult0, Mult1, S0 and S1 control signals are stable.
Power-down
Clock Stop
Table 13.
Normal
State
t
t
POWERDN
STOP
t
CLKOFF
PwrDnB
0
1
1
StopB
X
0
1
W134M/W134S
Source
Clock
OFF
ON
ON
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Disabled
Enabled
Output
Ground
Buffer