W134 Cypress Semiconductor Corp., W134 Datasheet - Page 4

• Manufacturer Part Number: W134
• Description: 400 MHZ DRCG
• Manufacturer: Cypress Semiconductor Corp.

Table 1. Supported Pclk and Busclk Frequencies, by Gear Ratio
Figure 3 shows more details of the DDLL system architecture,
including the DRCG output enable and bypass modes.
Phase Detector Signals
The DRCG Phase Detector receives two inputs from the core
logic, PclkM (Pclk/M) and SynclkN (Synclk/N). The M and N
dividers in the core logic are chosen so that the frequencies of
PclkM and SynclkN are identical. The Phase Detector detects
the phase difference between the two input clocks, and drives
the DRCG Phase Aligner to null the input phase error through
the distributed loop. When the loop is locked, the input phase
error between PclkM and SynclkN is within the specification
t
Transition Section.
The Phase Detector aligns the rising edge of PclkM to the
rising edge of SynclkN. The duty cycle of the phase detector
input clocks will be within the specification DC
Table 13. Because the duty cycles of the two phase detector
input clocks will not necessarily be identical, the falling edges
of PclkM and SynclkN may not be aligned when the rising edg-
es are aligned.
The voltage levels of the PclkM and SynclkN signals are de-
termined by the controller. The pin VDDIPD is used as the
voltage reference for the phase detector inputs and should be
connected to the output voltage supply of the controller. In
some applications, the DRCG PLL output clock will be used
Document #: 38-07426 Rev. **
ERR,PD
67 MHz
100 MHz
133 MHz
150 MHz
200 MHz
given in Table 14 after the lock time given in the State
Pclk
267 MHz
400 MHz
W133
W158
W159
W161
W167
CY2210
2.0
RMC
Pclk
Figure 3. DDLL Including Details of DRCG
Refclk
IN,PD
given in
W134M/W134S
PLL
M
Gear
Ratio
Logic
356 MHz
400 MHz
N
1.5
Gear Ratio and Busclk
Phase
Align
D
Synclk
directly, by bypassing the Phase Aligner. If PclkM and SynclkN
are not used, those inputs must be grounded.
Selection Logic
Table 2 shows the logic for selecting the PLL prescaler and
feedback dividers to determine the multiply ratio for the PLL
from the input Refclk. Divider A sets the feedback and divider
B sets the prescaler, so the PLL output clock frequency is set
by: PLLclk=Refclk*A/B.
Table 2. PLL Divider Selection
Table 3 shows the logic for enabling the clock outputs, using
the StopB input signal. When StopB is HIGH, the DRCG is in
its normal mode, and Clk and ClkB are complementary out-
puts following the Phase Aligner output (PAclk). When StopB
is LOW, the DRCG is in the Clk Stop mode, the output clock
drivers are disabled (set to Hi-Z), and the Clk and ClkB settle
to the DC voltage V
V
X,STOP
Mult0
0
0
1
1
4
S0/S1 StopB
is set by an external resistor network.
Mult1
DLL
0
1
1
0
RAC
300 MHz
400 MHz
X,STOP
1.33
Busclk
16
A
9
6
8
W134M
as given in Table 14. The level of
B
2
1
1
3
W134M/W134S
267 MHz
400 MHz
16
A
4
6
8
1.0
W134S
Page 4 of 13
B
1
1
1
3